196 lines
8.3 KiB
C
196 lines
8.3 KiB
C
/* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __ASM_ARCH_MSM_IRQS_9615_H
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#define __ASM_ARCH_MSM_IRQS_9615_H
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/* MSM ACPU Interrupt Numbers */
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#define FIQ_START 16
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#define INT_DEBUG_TIMER_EXP (GIC_PPI_START + 1)
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#define INT_GP_TIMER_EXP (GIC_PPI_START + 2)
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#define INT_GP_TIMER2_EXP (GIC_PPI_START + 3)
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#define WDT0_ACCSCSSNBARK_INT (GIC_PPI_START + 4)
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#define WDT1_ACCSCSSNBARK_INT (GIC_PPI_START + 5)
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#define AVS_SVICINT (GIC_PPI_START + 6)
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#define AVS_SVICINTSWDONE (GIC_PPI_START + 7)
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#define CPU_DBGCPUXCOMMRXFULL (GIC_PPI_START + 8)
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#define CPU_DBGCPUXCOMMTXEMPTY (GIC_PPI_START + 9)
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#define INT_ARMQC_PERFMON (GIC_PPI_START + 10)
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#define SC_AVSCPUXDOWN (GIC_PPI_START + 11)
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#define SC_AVSCPUXUP (GIC_PPI_START + 12)
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#define SC_SICCPUXACGIRPTREQ (GIC_PPI_START + 13)
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#define SC_SICCPUXEXTFAULTIRPTREQ (GIC_PPI_START + 14)
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/* PPI 15 is unused */
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#define APCC_QGICACGIRPTREQ (GIC_SPI_START + 0)
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#define APCC_QGICL2PERFMONIRPTREQ (GIC_SPI_START + 1)
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#define SC_SICL2PERFMONIRPTREQ APCC_QGICL2PERFMONIRPTREQ
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#define APCC_QGICL2IRPTREQ (GIC_SPI_START + 2)
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#define APCC_QGICMPUIRPTREQ (GIC_SPI_START + 3)
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#define TLMM_MSM_DIR_CONN_IRQ_0 (GIC_SPI_START + 4)
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#define TLMM_MSM_DIR_CONN_IRQ_1 (GIC_SPI_START + 5)
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#define TLMM_MSM_DIR_CONN_IRQ_2 (GIC_SPI_START + 6)
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#define TLMM_MSM_DIR_CONN_IRQ_3 (GIC_SPI_START + 7)
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#define TLMM_MSM_DIR_CONN_IRQ_4 (GIC_SPI_START + 8)
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#define TLMM_MSM_DIR_CONN_IRQ_5 (GIC_SPI_START + 9)
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#define TLMM_MSM_DIR_CONN_IRQ_6 (GIC_SPI_START + 10)
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#define TLMM_MSM_DIR_CONN_IRQ_7 (GIC_SPI_START + 11)
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#define TLMM_MSM_DIR_CONN_IRQ_8 (GIC_SPI_START + 12)
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#define TLMM_MSM_DIR_CONN_IRQ_9 (GIC_SPI_START + 13)
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/* 14 Reserved */
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#define PM8018_SEC_IRQ_N (GIC_SPI_START + 15)
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#define TLMM_MSM_SUMMARY_IRQ (GIC_SPI_START + 16)
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#define SPDM_RT_1_IRQ (GIC_SPI_START + 17)
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#define SPDM_DIAG_IRQ (GIC_SPI_START + 18)
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#define RPM_APCC_CPU0_GP_HIGH_IRQ (GIC_SPI_START + 19)
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#define RPM_APCC_CPU0_GP_MEDIUM_IRQ (GIC_SPI_START + 20)
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#define RPM_APCC_CPU0_GP_LOW_IRQ (GIC_SPI_START + 21)
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#define RPM_APCC_CPU0_WAKE_UP_IRQ (GIC_SPI_START + 22)
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/* 23-28 Reserved */
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#define SSBI2_1_SC_CPU0_SECURE_IRQ (GIC_SPI_START + 29)
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#define SSBI2_1_SC_CPU0_NON_SECURE_IRQ (GIC_SPI_START + 30)
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/* 31 Reserved */
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#define MSMC_SC_PRI_CE_IRQ (GIC_SPI_START + 32)
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#define SLIMBUS0_CORE_EE1_IRQ (GIC_SPI_START + 33)
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#define SLIMBUS0_BAM_EE1_IRQ (GIC_SPI_START + 34)
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#define Q6FW_WDOG_EXPIRED_IRQ (GIC_SPI_START + 35)
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#define Q6SW_WDOG_EXPIRED_IRQ (GIC_SPI_START + 36)
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#define MSS_TO_APPS_IRQ_0 (GIC_SPI_START + 37)
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#define MSS_TO_APPS_IRQ_1 (GIC_SPI_START + 38)
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#define MSS_TO_APPS_IRQ_2 (GIC_SPI_START + 39)
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#define MSS_TO_APPS_IRQ_3 (GIC_SPI_START + 40)
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#define MSS_TO_APPS_IRQ_4 (GIC_SPI_START + 41)
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#define MSS_TO_APPS_IRQ_5 (GIC_SPI_START + 42)
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#define MSS_TO_APPS_IRQ_6 (GIC_SPI_START + 43)
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#define MSS_TO_APPS_IRQ_7 (GIC_SPI_START + 44)
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#define MSS_TO_APPS_IRQ_8 (GIC_SPI_START + 45)
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#define MSS_TO_APPS_IRQ_9 (GIC_SPI_START + 46)
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/* 47-84 Reserved */
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#define LPASS_SCSS_AUDIO_IF_OUT0_IRQ (GIC_SPI_START + 85)
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#define LPASS_SCSS_MIDI_IRQ (GIC_SPI_START + 86)
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#define LPASS_Q6SS_WDOG_EXPIRED (GIC_SPI_START + 87)
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#define LPASS_SCSS_GP_LOW_IRQ (GIC_SPI_START + 88)
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#define LPASS_SCSS_GP_MEDIUM_IRQ (GIC_SPI_START + 89)
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#define LPASS_SCSS_GP_HIGH_IRQ (GIC_SPI_START + 90)
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#define TOP_IMEM_IRQ (GIC_SPI_START + 91)
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#define FABRIC_SYS_IRQ (GIC_SPI_START + 92)
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/* 93 Reserved */
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#define USB1_HS_BAM_IRQ (GIC_SPI_START + 94)
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/* 95,96 unnamed */
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#define SDC2_BAM_IRQ (GIC_SPI_START + 97)
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#define SDC1_BAM_IRQ (GIC_SPI_START + 98)
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#define FABRIC_SPS_IRQ (GIC_SPI_START + 99)
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#define USB1_HS_IRQ (GIC_SPI_START + 100)
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/* 101,102 unnamed */
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#define SDC2_IRQ_0 (GIC_SPI_START + 103)
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#define SDC1_IRQ_0 (GIC_SPI_START + 104)
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#define SPS_BAM_DMA_IRQ (GIC_SPI_START + 105)
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#define SPS_SEC_VIOL_IRQ (GIC_SPI_START + 106)
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#define SPS_MTI_0 (GIC_SPI_START + 107)
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#define SPS_MTI_1 (GIC_SPI_START + 108)
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#define SPS_MTI_2 (GIC_SPI_START + 109)
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#define SPS_MTI_3 (GIC_SPI_START + 110)
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#define SPS_MTI_4 (GIC_SPI_START + 111)
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#define SPS_MTI_5 (GIC_SPI_START + 112)
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#define SPS_MTI_6 (GIC_SPI_START + 113)
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#define SPS_MTI_7 (GIC_SPI_START + 114)
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#define SPS_MTI_8 (GIC_SPI_START + 115)
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#define SPS_MTI_9 (GIC_SPI_START + 116)
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#define SPS_MTI_10 (GIC_SPI_START + 117)
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#define SPS_MTI_11 (GIC_SPI_START + 118)
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#define SPS_MTI_12 (GIC_SPI_START + 119)
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#define SPS_MTI_13 (GIC_SPI_START + 120)
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#define SPS_MTI_14 (GIC_SPI_START + 121)
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#define SPS_MTI_15 (GIC_SPI_START + 122)
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#define SPS_MTI_16 (GIC_SPI_START + 123)
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#define SPS_MTI_17 (GIC_SPI_START + 124)
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#define SPS_MTI_18 (GIC_SPI_START + 125)
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#define SPS_MTI_19 (GIC_SPI_START + 126)
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#define SPS_MTI_20 (GIC_SPI_START + 127)
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#define SPS_MTI_21 (GIC_SPI_START + 128)
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#define SPS_MTI_22 (GIC_SPI_START + 129)
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#define SPS_MTI_23 (GIC_SPI_START + 130)
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#define SPS_MTI_24 (GIC_SPI_START + 131)
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#define SPS_MTI_25 (GIC_SPI_START + 132)
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#define SPS_MTI_26 (GIC_SPI_START + 133)
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#define SPS_MTI_27 (GIC_SPI_START + 134)
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#define SPS_MTI_28 (GIC_SPI_START + 135)
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#define SPS_MTI_29 (GIC_SPI_START + 136)
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#define SPS_MTI_30 (GIC_SPI_START + 137)
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#define SPS_MTI_31 (GIC_SPI_START + 138)
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#define CSIPHY_0_4LN_IRQ (GIC_SPI_START + 139)
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#define CSIPHY_1_2LN_IRQ (GIC_SPI_START + 140)
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/* 141-145 Reserved */
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#define GSBI1_UARTDM_IRQ (GIC_SPI_START + 146)
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#define GSBI1_QUP_IRQ (GIC_SPI_START + 147)
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#define GSBI2_UARTDM_IRQ (GIC_SPI_START + 148)
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#define GSBI2_QUP_IRQ (GIC_SPI_START + 149)
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#define GSBI3_UARTDM_IRQ (GIC_SPI_START + 150)
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#define GSBI3_QUP_IRQ (GIC_SPI_START + 151)
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#define GSBI4_UARTDM_IRQ (GIC_SPI_START + 152)
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#define GSBI4_QUP_IRQ (GIC_SPI_START + 153)
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#define GSBI5_UARTDM_IRQ (GIC_SPI_START + 154)
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#define GSBI5_QUP_IRQ (GIC_SPI_START + 155)
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/* 156-167 Reserved */
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#define MSMC_SC_SEC_TMR_IRQ (GIC_SPI_START + 168)
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#define MSMC_SC_SEC_WDOG_BARK_IRQ (GIC_SPI_START + 169)
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#define ADM_0_SCSS_0_IRQ (GIC_SPI_START + 170)
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#define ADM_0_SCSS_1_IRQ (GIC_SPI_START + 171)
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#define ADM_0_SCSS_2_IRQ (GIC_SPI_START + 172)
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#define ADM_0_SCSS_3_IRQ (GIC_SPI_START + 173)
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/* 174 Reserved */
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#define CC_SCSS_WDT1CPU0BITEEXPIRED (GIC_SPI_START + 175)
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/* 176 Reserved */
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#define CC_SCSS_WDT0CPU0BITEEXPIRED (GIC_SPI_START + 177)
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#define TSENS_UPPER_LOWER_INT (GIC_SPI_START + 178)
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/* 179-182 Reserved */
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#define XPU_SUMMARY_IRQ (GIC_SPI_START + 183)
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#define BUS_EXCEPTION_SUMMARY_IRQ (GIC_SPI_START + 184)
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#define HSDDRX_EBI1CH0_IRQ (GIC_SPI_START + 185)
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/* 186-208 Reserved */
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#define A2_BAM_IRQ (GIC_SPI_START + 209)
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/* 210-215 Reserved */
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#define QDSS_ETB_IRQ (GIC_SPI_START + 216)
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/* 216 Reserved */
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#define QDSS_CTI2KPSS_CPU0_IRQ (GIC_SPI_START + 218)
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#define TLMM_MSM_DIR_CONN_IRQ_16 (GIC_SPI_START + 219)
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#define TLMM_MSM_DIR_CONN_IRQ_17 (GIC_SPI_START + 220)
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#define TLMM_MSM_DIR_CONN_IRQ_18 (GIC_SPI_START + 221)
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#define TLMM_MSM_DIR_CONN_IRQ_19 (GIC_SPI_START + 222)
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#define TLMM_MSM_DIR_CONN_IRQ_20 (GIC_SPI_START + 223)
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#define TLMM_MSM_DIR_CONN_IRQ_21 (GIC_SPI_START + 224)
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#define MSM_SPARE0_IRQ (GIC_SPI_START + 225)
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#define PMIC_SEC_IRQ_N (GIC_SPI_START + 226)
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#define USB_HSIC_BAM_IRQ (GIC_SPI_START + 231)
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#define USB_HSIC_IRQ (GIC_SPI_START + 232)
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#define NR_MSM_IRQS 288
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#define NR_GPIO_IRQS 88
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#define NR_PM8018_IRQS 256
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#define NR_WCD9XXX_IRQS 49
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#define NR_TABLA_IRQS NR_WCD9XXX_IRQS
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#define NR_BOARD_IRQS (NR_PM8018_IRQS + NR_WCD9XXX_IRQS)
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#define NR_MSM_GPIOS NR_GPIO_IRQS
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/* Backwards compatible IRQ macros. */
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#define INT_ADM_AARM ADM_0_SCSS_0_IRQ
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/* smd/smsm interrupts */
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#define INT_A9_M2A_0 MSS_TO_APPS_IRQ_0
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#define INT_A9_M2A_5 MSS_TO_APPS_IRQ_1
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#define INT_ADSP_A11 LPASS_SCSS_GP_HIGH_IRQ
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#define INT_ADSP_A11_SMSM LPASS_SCSS_GP_MEDIUM_IRQ
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#endif
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