400 lines
11 KiB
C
400 lines
11 KiB
C
/* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/platform_device.h>
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#include <linux/gpio.h>
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#include <linux/bootmem.h>
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#include <asm/mach-types.h>
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#include <asm/mach/mmc.h>
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#include <mach/msm_bus_board.h>
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#include <mach/board.h>
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#include <mach/gpiomux.h>
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#include "devices.h"
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#include "board-8064.h"
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#include "board-storage-common-a.h"
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/* APQ8064 has 4 SDCC controllers */
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enum sdcc_controllers {
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SDCC1,
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SDCC2,
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SDCC3,
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SDCC4,
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MAX_SDCC_CONTROLLER
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};
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/* All SDCC controllers require VDD/VCC voltage */
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static struct msm_mmc_reg_data mmc_vdd_reg_data[MAX_SDCC_CONTROLLER] = {
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/* SDCC1 : eMMC card connected */
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[SDCC1] = {
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.name = "sdc_vdd",
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.high_vol_level = 2950000,
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.low_vol_level = 2950000,
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.always_on = 1,
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.lpm_sup = 1,
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.lpm_uA = 9000,
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.hpm_uA = 200000, /* 200mA */
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},
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/* SDCC3 : External card slot connected */
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[SDCC3] = {
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.name = "sdc_vdd",
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.high_vol_level = 2950000,
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.low_vol_level = 2950000,
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.hpm_uA = 800000, /* 800mA */
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}
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};
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/* SDCC controllers may require voting for VDD IO voltage */
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static struct msm_mmc_reg_data mmc_vdd_io_reg_data[MAX_SDCC_CONTROLLER] = {
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/* SDCC1 : eMMC card connected */
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[SDCC1] = {
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.name = "sdc_vdd_io",
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.always_on = 1,
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.high_vol_level = 1800000,
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.low_vol_level = 1800000,
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.hpm_uA = 200000, /* 200mA */
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},
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/* SDCC3 : External card slot connected */
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[SDCC3] = {
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.name = "sdc_vdd_io",
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.high_vol_level = 2950000,
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.low_vol_level = 1850000,
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.always_on = 1,
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.lpm_sup = 1,
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/* Max. Active current required is 16 mA */
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.hpm_uA = 16000,
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/*
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* Sleep current required is ~300 uA. But min. vote can be
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* in terms of mA (min. 1 mA). So let's vote for 2 mA
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* during sleep.
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*/
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.lpm_uA = 2000,
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}
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};
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static struct msm_mmc_slot_reg_data mmc_slot_vreg_data[MAX_SDCC_CONTROLLER] = {
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/* SDCC1 : eMMC card connected */
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[SDCC1] = {
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.vdd_data = &mmc_vdd_reg_data[SDCC1],
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.vdd_io_data = &mmc_vdd_io_reg_data[SDCC1],
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},
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/* SDCC3 : External card slot connected */
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[SDCC3] = {
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.vdd_data = &mmc_vdd_reg_data[SDCC3],
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.vdd_io_data = &mmc_vdd_io_reg_data[SDCC3],
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}
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};
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/* SDC1 pad data */
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static struct msm_mmc_pad_drv sdc1_pad_drv_on_cfg[] = {
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{TLMM_HDRV_SDC1_CLK, GPIO_CFG_16MA},
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{TLMM_HDRV_SDC1_CMD, GPIO_CFG_10MA},
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{TLMM_HDRV_SDC1_DATA, GPIO_CFG_10MA}
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};
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static struct msm_mmc_pad_drv sdc1_pad_drv_off_cfg[] = {
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{TLMM_HDRV_SDC1_CLK, GPIO_CFG_2MA},
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{TLMM_HDRV_SDC1_CMD, GPIO_CFG_2MA},
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{TLMM_HDRV_SDC1_DATA, GPIO_CFG_2MA}
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};
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static struct msm_mmc_pad_pull sdc1_pad_pull_on_cfg[] = {
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{TLMM_PULL_SDC1_CLK, GPIO_CFG_NO_PULL},
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{TLMM_PULL_SDC1_CMD, GPIO_CFG_PULL_UP},
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{TLMM_PULL_SDC1_DATA, GPIO_CFG_PULL_UP}
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};
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static struct msm_mmc_pad_pull sdc1_pad_pull_off_cfg[] = {
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{TLMM_PULL_SDC1_CLK, GPIO_CFG_NO_PULL},
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{TLMM_PULL_SDC1_CMD, GPIO_CFG_PULL_UP},
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{TLMM_PULL_SDC1_DATA, GPIO_CFG_PULL_UP}
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};
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/* SDC3 pad data */
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static struct msm_mmc_pad_drv sdc3_pad_drv_on_cfg[] = {
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{TLMM_HDRV_SDC3_CLK, GPIO_CFG_8MA},
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{TLMM_HDRV_SDC3_CMD, GPIO_CFG_8MA},
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{TLMM_HDRV_SDC3_DATA, GPIO_CFG_8MA}
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};
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static struct msm_mmc_pad_drv sdc3_pad_drv_off_cfg[] = {
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{TLMM_HDRV_SDC3_CLK, GPIO_CFG_2MA},
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{TLMM_HDRV_SDC3_CMD, GPIO_CFG_2MA},
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{TLMM_HDRV_SDC3_DATA, GPIO_CFG_2MA}
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};
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static struct msm_mmc_pad_pull sdc3_pad_pull_on_cfg[] = {
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{TLMM_PULL_SDC3_CLK, GPIO_CFG_NO_PULL},
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{TLMM_PULL_SDC3_CMD, GPIO_CFG_PULL_UP},
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{TLMM_PULL_SDC3_DATA, GPIO_CFG_PULL_UP}
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};
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static struct msm_mmc_pad_pull sdc3_pad_pull_off_cfg[] = {
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{TLMM_PULL_SDC3_CLK, GPIO_CFG_NO_PULL},
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{TLMM_PULL_SDC3_CMD, GPIO_CFG_PULL_UP},
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{TLMM_PULL_SDC3_DATA, GPIO_CFG_PULL_UP}
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};
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static struct msm_mmc_pad_pull_data mmc_pad_pull_data[MAX_SDCC_CONTROLLER] = {
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[SDCC1] = {
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.on = sdc1_pad_pull_on_cfg,
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.off = sdc1_pad_pull_off_cfg,
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.size = ARRAY_SIZE(sdc1_pad_pull_on_cfg)
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},
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[SDCC3] = {
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.on = sdc3_pad_pull_on_cfg,
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.off = sdc3_pad_pull_off_cfg,
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.size = ARRAY_SIZE(sdc3_pad_pull_on_cfg)
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},
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};
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static struct msm_mmc_pad_drv_data mmc_pad_drv_data[MAX_SDCC_CONTROLLER] = {
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[SDCC1] = {
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.on = sdc1_pad_drv_on_cfg,
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.off = sdc1_pad_drv_off_cfg,
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.size = ARRAY_SIZE(sdc1_pad_drv_on_cfg)
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},
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[SDCC3] = {
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.on = sdc3_pad_drv_on_cfg,
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.off = sdc3_pad_drv_off_cfg,
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.size = ARRAY_SIZE(sdc3_pad_drv_on_cfg)
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},
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};
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static struct msm_mmc_pad_data mmc_pad_data[MAX_SDCC_CONTROLLER] = {
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[SDCC1] = {
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.pull = &mmc_pad_pull_data[SDCC1],
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.drv = &mmc_pad_drv_data[SDCC1]
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},
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[SDCC3] = {
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.pull = &mmc_pad_pull_data[SDCC3],
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.drv = &mmc_pad_drv_data[SDCC3]
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},
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};
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static struct msm_mmc_gpio sdc2_gpio[] = {
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{59, "sdc2_clk"},
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{57, "sdc2_cmd"},
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{62, "sdc2_dat_0"},
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{61, "sdc2_dat_1"},
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{60, "sdc2_dat_2"},
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{58, "sdc2_dat_3"},
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};
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static struct msm_mmc_gpio sdc4_gpio[] = {
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{68, "sdc4_clk"},
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{67, "sdc4_cmd"},
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{66, "sdc4_dat_0"},
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{65, "sdc4_dat_1"},
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{64, "sdc4_dat_2"},
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{63, "sdc4_dat_3"},
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};
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static struct msm_mmc_gpio_data mmc_gpio_data[MAX_SDCC_CONTROLLER] = {
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[SDCC2] = {
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.gpio = sdc2_gpio,
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.size = ARRAY_SIZE(sdc2_gpio),
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},
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[SDCC4] = {
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.gpio = sdc4_gpio,
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.size = ARRAY_SIZE(sdc4_gpio),
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}
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};
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static struct msm_mmc_pin_data mmc_slot_pin_data[MAX_SDCC_CONTROLLER] = {
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[SDCC1] = {
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.pad_data = &mmc_pad_data[SDCC1],
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},
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[SDCC2] = {
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.is_gpio = 1,
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.gpio_data = &mmc_gpio_data[SDCC2],
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},
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[SDCC3] = {
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.pad_data = &mmc_pad_data[SDCC3],
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},
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[SDCC4] = {
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.is_gpio = 1,
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.gpio_data = &mmc_gpio_data[SDCC4],
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},
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};
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#define MSM_MPM_PIN_SDC1_DAT1 17
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#define MSM_MPM_PIN_SDC3_DAT1 21
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#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
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static unsigned int sdc1_sup_clk_rates[] = {
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400000, 24000000, 48000000, 96000000
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};
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static struct mmc_platform_data sdc1_data = {
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.ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
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#ifdef CONFIG_MMC_MSM_SDC1_8_BIT_SUPPORT
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.mmc_bus_width = MMC_CAP_8_BIT_DATA,
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#else
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.mmc_bus_width = MMC_CAP_4_BIT_DATA,
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#endif
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.sup_clk_table = sdc1_sup_clk_rates,
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.sup_clk_cnt = ARRAY_SIZE(sdc1_sup_clk_rates),
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.nonremovable = 1,
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.pin_data = &mmc_slot_pin_data[SDCC1],
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.vreg_data = &mmc_slot_vreg_data[SDCC1],
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.uhs_caps = MMC_CAP_1_8V_DDR | MMC_CAP_UHS_DDR50,
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.uhs_caps2 = MMC_CAP2_HS200_1_8V_SDR,
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.mpm_sdiowakeup_int = MSM_MPM_PIN_SDC1_DAT1,
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.msm_bus_voting_data = &sps_to_ddr_bus_voting_data,
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};
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static struct mmc_platform_data *apq8064_sdc1_pdata = &sdc1_data;
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#else
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static struct mmc_platform_data *apq8064_sdc1_pdata;
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#endif
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#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
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static unsigned int sdc2_sup_clk_rates[] = {
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400000, 24000000, 48000000
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};
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static struct mmc_platform_data sdc2_data = {
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.ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
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.mmc_bus_width = MMC_CAP_4_BIT_DATA,
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.sup_clk_table = sdc2_sup_clk_rates,
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.sup_clk_cnt = ARRAY_SIZE(sdc2_sup_clk_rates),
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.pin_data = &mmc_slot_pin_data[SDCC2],
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.sdiowakeup_irq = MSM_GPIO_TO_INT(61),
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.msm_bus_voting_data = &sps_to_ddr_bus_voting_data,
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};
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static struct mmc_platform_data *apq8064_sdc2_pdata = &sdc2_data;
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#else
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static struct mmc_platform_data *apq8064_sdc2_pdata;
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#endif
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#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
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static unsigned int sdc3_sup_clk_rates[] = {
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400000, 24000000, 48000000, 96000000, 192000000
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};
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static struct mmc_platform_data sdc3_data = {
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.ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
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.mmc_bus_width = MMC_CAP_4_BIT_DATA,
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.sup_clk_table = sdc3_sup_clk_rates,
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.sup_clk_cnt = ARRAY_SIZE(sdc3_sup_clk_rates),
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.pin_data = &mmc_slot_pin_data[SDCC3],
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.vreg_data = &mmc_slot_vreg_data[SDCC3],
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.wpswitch_gpio = PM8921_GPIO_PM_TO_SYS(17),
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.is_wpswitch_active_low = true,
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.status_gpio = 26,
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.status_irq = MSM_GPIO_TO_INT(26),
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.irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
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.is_status_gpio_active_low = 1,
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.xpc_cap = 1,
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.uhs_caps = (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
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MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 |
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MMC_CAP_UHS_SDR104 | MMC_CAP_MAX_CURRENT_800),
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.mpm_sdiowakeup_int = MSM_MPM_PIN_SDC3_DAT1,
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.msm_bus_voting_data = &sps_to_ddr_bus_voting_data,
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};
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static struct mmc_platform_data *apq8064_sdc3_pdata = &sdc3_data;
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#else
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static struct mmc_platform_data *apq8064_sdc3_pdata;
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#endif
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#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
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static unsigned int sdc4_sup_clk_rates[] = {
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400000, 24000000, 48000000
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};
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static struct mmc_platform_data sdc4_data = {
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.ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
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.mmc_bus_width = MMC_CAP_4_BIT_DATA,
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.sup_clk_table = sdc4_sup_clk_rates,
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.sup_clk_cnt = ARRAY_SIZE(sdc4_sup_clk_rates),
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.pin_data = &mmc_slot_pin_data[SDCC4],
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.sdiowakeup_irq = MSM_GPIO_TO_INT(65),
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.msm_bus_voting_data = &sps_to_ddr_bus_voting_data,
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};
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static struct mmc_platform_data *apq8064_sdc4_pdata = &sdc4_data;
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#else
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static struct mmc_platform_data *apq8064_sdc4_pdata;
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#endif
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void __init apq8064_init_mmc(void)
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{
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if (apq8064_sdc1_pdata)
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apq8064_add_sdcc(1, apq8064_sdc1_pdata);
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if (apq8064_sdc2_pdata)
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apq8064_add_sdcc(2, apq8064_sdc2_pdata);
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if (apq8064_sdc3_pdata) {
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if (machine_is_mpq8064_hrd() || machine_is_mpq8064_dtv()) {
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apq8064_sdc3_pdata->uhs_caps &= ~(MMC_CAP_UHS_SDR12 |
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MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_DDR50 |
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MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104);
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}
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if (!machine_is_apq8064_cdp()) {
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apq8064_sdc3_pdata->wpswitch_gpio = 0;
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apq8064_sdc3_pdata->is_wpswitch_active_low = false;
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}
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if (machine_is_mpq8064_cdp() || machine_is_mpq8064_hrd() ||
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machine_is_mpq8064_dtv()) {
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int rc;
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struct pm_gpio sd_card_det_init_cfg = {
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.direction = PM_GPIO_DIR_IN,
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.output_buffer = PM_GPIO_OUT_BUF_CMOS,
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.pull = PM_GPIO_PULL_UP_30,
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.vin_sel = PM_GPIO_VIN_S4,
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.out_strength = PM_GPIO_STRENGTH_NO,
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.function = PM_GPIO_FUNC_NORMAL,
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};
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apq8064_sdc3_pdata->status_gpio =
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PM8921_GPIO_PM_TO_SYS(31);
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apq8064_sdc3_pdata->status_irq =
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PM8921_GPIO_IRQ(PM8921_IRQ_BASE, 31);
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rc = pm8xxx_gpio_config(apq8064_sdc3_pdata->status_gpio,
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&sd_card_det_init_cfg);
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if (rc) {
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pr_info("%s: SD_CARD_DET GPIO%d config "
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"failed(%d)\n", __func__,
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apq8064_sdc3_pdata->status_gpio, rc);
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apq8064_sdc3_pdata->status_gpio = 0;
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apq8064_sdc3_pdata->status_irq = 0;
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}
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}
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if (machine_is_apq8064_cdp()) {
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int i;
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for (i = 0;
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i < apq8064_sdc3_pdata->pin_data->pad_data->\
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drv->size;
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i++)
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apq8064_sdc3_pdata->pin_data->pad_data->\
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drv->on[i].val = GPIO_CFG_10MA;
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}
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if (machine_is_mpq8064_hrd() || machine_is_mpq8064_dtv()) {
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apq8064_sdc3_pdata->pin_data->pad_data->\
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drv->on[0].val = GPIO_CFG_16MA;
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apq8064_sdc3_pdata->pin_data->pad_data->\
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drv->on[1].val = GPIO_CFG_10MA;
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apq8064_sdc3_pdata->pin_data->pad_data->\
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drv->on[2].val = GPIO_CFG_10MA;
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}
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apq8064_add_sdcc(3, apq8064_sdc3_pdata);
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}
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if (apq8064_sdc4_pdata)
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apq8064_add_sdcc(4, apq8064_sdc4_pdata);
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}
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