164 lines
4.7 KiB
C
164 lines
4.7 KiB
C
/*
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* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define pr_fmt(fmt) "%s: " fmt, __func__
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/errno.h>
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#include <linux/platform_device.h>
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#include <linux/regulator/consumer.h>
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#include <mach/msm_bus.h>
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#include <mach/msm_bus_board.h>
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#include <mach/clk-provider.h>
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#include <mach/rpm-regulator-smd.h>
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#include "acpuclock-cortex.h"
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#define RCG_CONFIG_PGM_DATA_BIT BIT(11)
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#define RCG_CONFIG_PGM_ENA_BIT BIT(10)
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#define GPLL0_TO_A5_ALWAYS_ENABLE BIT(18)
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static struct msm_bus_paths bw_level_tbl[] = {
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[0] = BW_MBPS(152), /* At least 19 MHz on bus. */
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[1] = BW_MBPS(264), /* At least 33 MHz on bus. */
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[2] = BW_MBPS(528), /* At least 66 MHz on bus. */
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[3] = BW_MBPS(664), /* At least 83 MHz on bus. */
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[4] = BW_MBPS(1064), /* At least 133 MHz on bus. */
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[5] = BW_MBPS(1328), /* At least 166 MHz on bus. */
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[6] = BW_MBPS(2128), /* At least 266 MHz on bus. */
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[7] = BW_MBPS(2664), /* At least 333 MHz on bus. */
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};
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static struct msm_bus_scale_pdata bus_client_pdata = {
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.usecase = bw_level_tbl,
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.num_usecases = ARRAY_SIZE(bw_level_tbl),
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.active_only = 1,
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.name = "acpuclock",
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};
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/* TODO:
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* 1) Update MX voltage when they are avaiable
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* 2) Update bus bandwidth
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*/
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static struct clkctl_acpu_speed acpu_freq_tbl[] = {
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{ 0, 19200, CXO, 0, 0, LVL_LOW, 950000, 0 },
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{ 1, 300000, PLL0, 1, 2, LVL_LOW, 950000, 4 },
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{ 1, 600000, PLL0, 1, 0, LVL_NOM, 950000, 4 },
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{ 1, 748800, ACPUPLL, 5, 0, LVL_HIGH, 1050000, 7 },
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{ 1, 998400, ACPUPLL, 5, 0, LVL_HIGH, 1050000, 7 },
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{ 0 }
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};
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static struct acpuclk_drv_data drv_data = {
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.freq_tbl = acpu_freq_tbl,
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.bus_scale = &bus_client_pdata,
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.vdd_max_cpu = LVL_HIGH,
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.vdd_max_mem = 1050000,
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.src_clocks = {
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[PLL0].name = "pll0",
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[ACPUPLL].name = "pll14",
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},
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.reg_data = {
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.cfg_src_mask = BM(2, 0),
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.cfg_src_shift = 0,
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.cfg_div_mask = BM(7, 3),
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.cfg_div_shift = 3,
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.update_mask = RCG_CONFIG_PGM_DATA_BIT | RCG_CONFIG_PGM_ENA_BIT,
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.poll_mask = RCG_CONFIG_PGM_DATA_BIT,
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},
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.power_collapse_khz = 300000,
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.wait_for_irq_khz = 300000,
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};
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static int __init acpuclk_9625_probe(struct platform_device *pdev)
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{
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struct resource *res;
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u32 regval, i;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rcg_base");
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if (!res)
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return -EINVAL;
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drv_data.apcs_rcg_config = devm_ioremap(&pdev->dev, res->start,
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resource_size(res));
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if (!drv_data.apcs_rcg_config)
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return -ENOMEM;
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drv_data.apcs_rcg_cmd = drv_data.apcs_rcg_config;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwr_base");
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if (!res)
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return -EINVAL;
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drv_data.apcs_cpu_pwr_ctl = ioremap(res->start, resource_size(res));
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if (!drv_data.apcs_cpu_pwr_ctl)
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return -ENOMEM;
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drv_data.vdd_cpu = devm_regulator_get(&pdev->dev, "a5_cpu");
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if (IS_ERR(drv_data.vdd_cpu)) {
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dev_err(&pdev->dev, "regulator for %s get failed\n", "a5_cpu");
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return PTR_ERR(drv_data.vdd_cpu);
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}
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drv_data.vdd_mem = devm_regulator_get(&pdev->dev, "a5_mem");
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if (IS_ERR(drv_data.vdd_mem)) {
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dev_err(&pdev->dev, "regulator for %s get failed\n", "a5_mem");
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return PTR_ERR(drv_data.vdd_mem);
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}
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for (i = 0; i < NUM_SRC; i++) {
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if (!drv_data.src_clocks[i].name)
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continue;
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drv_data.src_clocks[i].clk =
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devm_clk_get(&pdev->dev, drv_data.src_clocks[i].name);
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if (IS_ERR(drv_data.src_clocks[i].clk)) {
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dev_err(&pdev->dev, "Unable to get clock %s\n",
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drv_data.src_clocks[i].name);
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return -EPROBE_DEFER;
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}
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}
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/* Disable hardware gating of gpll0 to A5SS */
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regval = readl_relaxed(drv_data.apcs_cpu_pwr_ctl);
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regval |= GPLL0_TO_A5_ALWAYS_ENABLE;
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writel_relaxed(regval, drv_data.apcs_cpu_pwr_ctl);
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/* Enable the always on source */
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clk_prepare_enable(drv_data.src_clocks[PLL0].clk);
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return acpuclk_cortex_init(pdev, &drv_data);
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}
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static struct of_device_id acpuclk_9625_match_table[] = {
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{.compatible = "qcom,acpuclk-9625"},
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{}
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};
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static struct platform_driver acpuclk_9625_driver = {
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.driver = {
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.name = "acpuclk-9625",
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.of_match_table = acpuclk_9625_match_table,
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.owner = THIS_MODULE,
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},
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};
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static int __init acpuclk_9625_init(void)
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{
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return platform_driver_probe(&acpuclk_9625_driver, acpuclk_9625_probe);
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}
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device_initcall(acpuclk_9625_init);
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