234 lines
9.4 KiB
C
234 lines
9.4 KiB
C
/*
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* Copyright (c) 2011-2013, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <mach/rpm-regulator.h>
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#include <mach/msm_bus_board.h>
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#include <mach/msm_bus.h>
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#include "acpuclock.h"
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#include "acpuclock-krait.h"
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static struct hfpll_data hfpll_data __initdata = {
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.mode_offset = 0x00,
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.l_offset = 0x08,
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.m_offset = 0x0C,
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.n_offset = 0x10,
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.config_offset = 0x04,
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.config_val = 0x7845C665,
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.has_droop_ctl = true,
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.droop_offset = 0x14,
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.droop_val = 0x0108C000,
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.low_vdd_l_max = 22,
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.nom_vdd_l_max = 42,
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.vdd[HFPLL_VDD_NONE] = 0,
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.vdd[HFPLL_VDD_LOW] = 945000,
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.vdd[HFPLL_VDD_NOM] = 1050000,
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.vdd[HFPLL_VDD_HIGH] = 1150000,
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};
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static struct scalable scalable[] __initdata = {
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[CPU0] = {
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.hfpll_phys_base = 0x00903200,
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.aux_clk_sel_phys = 0x02088014,
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.aux_clk_sel = 3,
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.sec_clk_sel = 2,
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.l2cpmr_iaddr = 0x4501,
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.vreg[VREG_CORE] = { "krait0", 1300000 },
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.vreg[VREG_MEM] = { "krait0_mem", 1150000 },
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.vreg[VREG_DIG] = { "krait0_dig", 1150000 },
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.vreg[VREG_HFPLL_A] = { "krait0_s8", 2050000 },
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.vreg[VREG_HFPLL_B] = { "krait0_l23", 1800000 },
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},
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[CPU1] = {
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.hfpll_phys_base = 0x00903300,
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.aux_clk_sel_phys = 0x02098014,
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.aux_clk_sel = 3,
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.sec_clk_sel = 2,
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.l2cpmr_iaddr = 0x5501,
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.vreg[VREG_CORE] = { "krait1", 1300000 },
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.vreg[VREG_MEM] = { "krait1_mem", 1150000 },
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.vreg[VREG_DIG] = { "krait1_dig", 1150000 },
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.vreg[VREG_HFPLL_A] = { "krait1_s8", 2050000 },
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.vreg[VREG_HFPLL_B] = { "krait1_l23", 1800000 },
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},
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[L2] = {
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.hfpll_phys_base = 0x00903400,
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.aux_clk_sel_phys = 0x02011028,
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.aux_clk_sel = 3,
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.sec_clk_sel = 2,
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.l2cpmr_iaddr = 0x0500,
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.vreg[VREG_HFPLL_A] = { "l2_s8", 2050000 },
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.vreg[VREG_HFPLL_B] = { "l2_l23", 1800000 },
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},
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};
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static struct msm_bus_paths bw_level_tbl[] __initdata = {
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[0] = BW_MBPS(640), /* At least 80 MHz on bus. */
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[1] = BW_MBPS(1064), /* At least 133 MHz on bus. */
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[2] = BW_MBPS(1600), /* At least 200 MHz on bus. */
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[3] = BW_MBPS(2128), /* At least 266 MHz on bus. */
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[4] = BW_MBPS(3200), /* At least 400 MHz on bus. */
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[5] = BW_MBPS(3600), /* At least 450 MHz on bus. */
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[6] = BW_MBPS(3936), /* At least 492 MHz on bus. */
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};
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static struct msm_bus_scale_pdata bus_scale_data __initdata = {
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.usecase = bw_level_tbl,
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.num_usecases = ARRAY_SIZE(bw_level_tbl),
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.active_only = 1,
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.name = "acpuclk-8960",
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};
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static struct l2_level l2_freq_tbl[] __initdata = {
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[0] = { { 384000, PLL_8, 0, 0x00 }, 1050000, 1050000, 1 },
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[1] = { { 432000, HFPLL, 2, 0x20 }, 1050000, 1050000, 2 },
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[2] = { { 486000, HFPLL, 2, 0x24 }, 1050000, 1050000, 2 },
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[3] = { { 540000, HFPLL, 2, 0x28 }, 1050000, 1050000, 2 },
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[4] = { { 594000, HFPLL, 1, 0x16 }, 1050000, 1050000, 2 },
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[5] = { { 648000, HFPLL, 1, 0x18 }, 1050000, 1050000, 4 },
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[6] = { { 702000, HFPLL, 1, 0x1A }, 1050000, 1050000, 4 },
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[7] = { { 756000, HFPLL, 1, 0x1C }, 1150000, 1150000, 4 },
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[8] = { { 810000, HFPLL, 1, 0x1E }, 1150000, 1150000, 4 },
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[9] = { { 864000, HFPLL, 1, 0x20 }, 1150000, 1150000, 4 },
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[10] = { { 918000, HFPLL, 1, 0x22 }, 1150000, 1150000, 6 },
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[11] = { { 972000, HFPLL, 1, 0x24 }, 1150000, 1150000, 6 },
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[12] = { { 1026000, HFPLL, 1, 0x26 }, 1150000, 1150000, 6 },
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[13] = { { 1080000, HFPLL, 1, 0x28 }, 1150000, 1150000, 6 },
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[14] = { { 1134000, HFPLL, 1, 0x2A }, 1150000, 1150000, 6 },
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[15] = { { 1188000, HFPLL, 1, 0x2C }, 1150000, 1150000, 6 },
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[16] = { { 1242000, HFPLL, 1, 0x2E }, 1150000, 1150000, 6 },
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[17] = { { 1296000, HFPLL, 1, 0x30 }, 1150000, 1150000, 6 },
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[18] = { { 1350000, HFPLL, 1, 0x32 }, 1150000, 1150000, 6 },
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{ }
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};
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#define AVS(x) .avsdscr_setting = (x)
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static struct acpu_level acpu_freq_tbl_slow[] __initdata = {
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{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000, AVS(0x40001F) },
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{ 0, { 432000, HFPLL, 2, 0x20 }, L2(6), 975000 },
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{ 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 975000 },
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{ 0, { 540000, HFPLL, 2, 0x28 }, L2(6), 1000000 },
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{ 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 1000000 },
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{ 0, { 648000, HFPLL, 1, 0x18 }, L2(6), 1025000 },
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{ 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 1025000 },
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{ 0, { 756000, HFPLL, 1, 0x1C }, L2(6), 1075000 },
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{ 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 1075000 },
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{ 0, { 864000, HFPLL, 1, 0x20 }, L2(6), 1100000 },
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{ 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 1100000 },
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{ 0, { 972000, HFPLL, 1, 0x24 }, L2(6), 1125000 },
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{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 1125000 },
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{ 0, { 1080000, HFPLL, 1, 0x28 }, L2(18), 1175000, AVS(0x400015) },
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{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(18), 1175000, AVS(0x400015) },
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{ 0, { 1188000, HFPLL, 1, 0x2C }, L2(18), 1200000, AVS(0x400015) },
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{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(18), 1200000, AVS(0x400015) },
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{ 0, { 1296000, HFPLL, 1, 0x30 }, L2(18), 1225000, AVS(0x400015) },
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{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(18), 1225000, AVS(0x400015) },
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{ 0, { 1404000, HFPLL, 1, 0x34 }, L2(18), 1237500, AVS(0x400015) },
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{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(18), 1237500, AVS(0x100018) },
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{ 1, { 1512000, HFPLL, 1, 0x38 }, L2(18), 1250000, AVS(0x400012) },
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{ 0, { 0 } }
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};
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static struct acpu_level acpu_freq_tbl_nom[] __initdata = {
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{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000, AVS(0x40007F) },
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{ 0, { 432000, HFPLL, 2, 0x20 }, L2(6), 925000 },
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{ 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 925000 },
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{ 0, { 540000, HFPLL, 2, 0x28 }, L2(6), 950000 },
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{ 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 950000 },
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{ 0, { 648000, HFPLL, 1, 0x18 }, L2(6), 975000 },
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{ 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 975000 },
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{ 0, { 756000, HFPLL, 1, 0x1C }, L2(6), 1025000 },
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{ 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 1025000 },
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{ 0, { 864000, HFPLL, 1, 0x20 }, L2(6), 1050000 },
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{ 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 1050000 },
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{ 0, { 972000, HFPLL, 1, 0x24 }, L2(6), 1075000 },
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{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 1075000 },
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{ 0, { 1080000, HFPLL, 1, 0x28 }, L2(18), 1125000, AVS(0x400015) },
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{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(18), 1125000, AVS(0x400015) },
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{ 0, { 1188000, HFPLL, 1, 0x2C }, L2(18), 1150000, AVS(0x400015) },
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{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(18), 1150000, AVS(0x400015) },
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{ 0, { 1296000, HFPLL, 1, 0x30 }, L2(18), 1175000, AVS(0x400015) },
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{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(18), 1175000, AVS(0x400015) },
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{ 0, { 1404000, HFPLL, 1, 0x34 }, L2(18), 1187500, AVS(0x400015) },
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{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(18), 1187500, AVS(0x100018) },
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{ 1, { 1512000, HFPLL, 1, 0x38 }, L2(18), 1200000, AVS(0x400012) },
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{ 0, { 0 } }
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};
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static struct acpu_level acpu_freq_tbl_fast[] __initdata = {
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{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 850000, AVS(0x4000FF) },
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{ 0, { 432000, HFPLL, 2, 0x20 }, L2(6), 875000 },
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{ 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 875000 },
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{ 0, { 540000, HFPLL, 2, 0x28 }, L2(6), 900000 },
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{ 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 900000 },
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{ 0, { 648000, HFPLL, 1, 0x18 }, L2(6), 925000 },
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{ 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 925000 },
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{ 0, { 756000, HFPLL, 1, 0x1C }, L2(6), 975000 },
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{ 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 975000 },
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{ 0, { 864000, HFPLL, 1, 0x20 }, L2(6), 1000000 },
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{ 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 1000000 },
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{ 0, { 972000, HFPLL, 1, 0x24 }, L2(6), 1025000 },
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{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 1025000 },
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{ 0, { 1080000, HFPLL, 1, 0x28 }, L2(18), 1075000, AVS(0x10001B) },
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{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(18), 1075000, AVS(0x10001B) },
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{ 0, { 1188000, HFPLL, 1, 0x2C }, L2(18), 1100000, AVS(0x10001B) },
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{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(18), 1100000, AVS(0x10001B) },
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{ 0, { 1296000, HFPLL, 1, 0x30 }, L2(18), 1125000, AVS(0x10001B) },
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{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(18), 1125000, AVS(0x400012) },
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{ 0, { 1404000, HFPLL, 1, 0x34 }, L2(18), 1137500, AVS(0x400012) },
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{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(18), 1137500, AVS(0x400012) },
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{ 1, { 1512000, HFPLL, 1, 0x38 }, L2(18), 1150000, AVS(0x400012) },
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{ 0, { 0 } }
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};
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static struct pvs_table pvs_tables[NUM_SPEED_BINS][NUM_PVS] __initdata = {
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[0][PVS_SLOW] = { acpu_freq_tbl_slow, sizeof(acpu_freq_tbl_slow), 0 },
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[0][PVS_NOMINAL] = { acpu_freq_tbl_nom, sizeof(acpu_freq_tbl_nom), 25000 },
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[0][PVS_FAST] = { acpu_freq_tbl_fast, sizeof(acpu_freq_tbl_fast), 25000 },
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};
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static struct acpuclk_krait_params acpuclk_8960_params __initdata = {
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.scalable = scalable,
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.scalable_size = sizeof(scalable),
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.hfpll_data = &hfpll_data,
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.pvs_tables = pvs_tables,
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.l2_freq_tbl = l2_freq_tbl,
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.l2_freq_tbl_size = sizeof(l2_freq_tbl),
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.bus_scale = &bus_scale_data,
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.pte_efuse_phys = 0x007000C0,
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.get_bin_info = get_krait_bin_format_a,
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.stby_khz = 384000,
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};
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static int __init acpuclk_8960_probe(struct platform_device *pdev)
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{
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return acpuclk_krait_init(&pdev->dev, &acpuclk_8960_params);
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}
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static struct platform_driver acpuclk_8960_driver = {
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.driver = {
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.name = "acpuclk-8960",
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.owner = THIS_MODULE,
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},
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};
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static int __init acpuclk_8960_init(void)
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{
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return platform_driver_probe(&acpuclk_8960_driver, acpuclk_8960_probe);
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}
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device_initcall(acpuclk_8960_init);
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