176 lines
5.2 KiB
C
176 lines
5.2 KiB
C
/*
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* Copyright (c) 2013, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define pr_fmt(fmt) "%s: " fmt, __func__
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/platform_device.h>
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#include <linux/regulator/consumer.h>
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#include <linux/regulator/cpr-regulator.h>
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#include <mach/clk-provider.h>
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#include <mach/msm_bus.h>
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#include <mach/msm_bus_board.h>
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#include <mach/rpm-regulator-smd.h>
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#include <mach/socinfo.h>
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#include "acpuclock-cortex.h"
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#define RCG_CONFIG_UPDATE_BIT BIT(0)
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static struct msm_bus_paths bw_level_tbl_8226[] = {
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[0] = BW_MBPS(152), /* At least 19 MHz on bus. */
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[1] = BW_MBPS(300), /* At least 37.5 MHz on bus. */
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[2] = BW_MBPS(400), /* At least 50 MHz on bus. */
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[3] = BW_MBPS(800), /* At least 100 MHz on bus. */
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[4] = BW_MBPS(1600), /* At least 200 MHz on bus. */
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[5] = BW_MBPS(2128), /* At least 266 MHz on bus. */
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[6] = BW_MBPS(3200), /* At least 400 MHz on bus. */
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[7] = BW_MBPS(4264), /* At least 533 MHz on bus. */
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};
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static struct msm_bus_paths bw_level_tbl_8610[] = {
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[0] = BW_MBPS(152), /* At least 19 MHz on bus. */
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[1] = BW_MBPS(300), /* At least 37.5 MHz on bus. */
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[2] = BW_MBPS(400), /* At least 50 MHz on bus. */
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[3] = BW_MBPS(800), /* At least 100 MHz on bus. */
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[4] = BW_MBPS(1600), /* At least 200 MHz on bus. */
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[5] = BW_MBPS(2128), /* At least 266 MHz on bus. */
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};
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static struct msm_bus_scale_pdata bus_client_pdata = {
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.usecase = bw_level_tbl_8226,
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.num_usecases = ARRAY_SIZE(bw_level_tbl_8226),
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.active_only = 1,
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.name = "acpuclock",
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};
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/* TODO:
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* 1) Update MX voltage when data is avaiable
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* 2) Update bus bandwidth
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* 3) Depending on Frodo version, may need minimum of LVL_NOM
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*/
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static struct clkctl_acpu_speed acpu_freq_tbl_8226[] = {
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{ 1, 300000, PLL0, 4, 2, CPR_CORNER_SVS, 0, 4 },
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{ 1, 384000, ACPUPLL, 5, 2, CPR_CORNER_SVS, 0, 4 },
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{ 1, 600000, PLL0, 4, 0, CPR_CORNER_NORMAL, 0, 6 },
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{ 1, 787200, ACPUPLL, 5, 0, CPR_CORNER_NORMAL, 0, 7 },
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{ 1, 998400, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 },
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{ 1, 1094400, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 },
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{ 0, 1190400, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 },
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{ 0 }
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};
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static struct clkctl_acpu_speed acpu_freq_tbl_8610[] = {
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{ 1, 300000, PLL0, 4, 2, CPR_CORNER_SVS, 0, 3 },
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{ 1, 384000, ACPUPLL, 5, 2, CPR_CORNER_SVS, 0, 3 },
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{ 1, 600000, PLL0, 4, 0, CPR_CORNER_NORMAL, 0, 4 },
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{ 1, 787200, ACPUPLL, 5, 0, CPR_CORNER_NORMAL, 0, 4 },
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{ 1, 998400, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 5 },
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{ 1, 1190400, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 5 },
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{ 0 }
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};
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static struct acpuclk_drv_data drv_data = {
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.freq_tbl = acpu_freq_tbl_8226,
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.bus_scale = &bus_client_pdata,
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.vdd_max_cpu = CPR_CORNER_TURBO,
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.src_clocks = {
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[PLL0].name = "gpll0",
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[ACPUPLL].name = "a7sspll",
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},
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.reg_data = {
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.cfg_src_mask = BM(10, 8),
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.cfg_src_shift = 8,
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.cfg_div_mask = BM(4, 0),
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.cfg_div_shift = 0,
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.update_mask = RCG_CONFIG_UPDATE_BIT,
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.poll_mask = RCG_CONFIG_UPDATE_BIT,
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},
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.power_collapse_khz = 300000,
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.wait_for_irq_khz = 300000,
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};
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static int __init acpuclk_a7_probe(struct platform_device *pdev)
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{
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struct resource *res;
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u32 i;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rcg_base");
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if (!res)
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return -EINVAL;
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drv_data.apcs_rcg_cmd = devm_ioremap(&pdev->dev, res->start,
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resource_size(res));
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if (!drv_data.apcs_rcg_cmd)
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return -ENOMEM;
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drv_data.apcs_rcg_config = drv_data.apcs_rcg_cmd + 4;
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drv_data.vdd_cpu = devm_regulator_get(&pdev->dev, "a7_cpu");
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if (IS_ERR(drv_data.vdd_cpu)) {
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dev_err(&pdev->dev, "regulator for %s get failed\n", "a7_cpu");
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return PTR_ERR(drv_data.vdd_cpu);
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}
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for (i = 0; i < NUM_SRC; i++) {
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if (!drv_data.src_clocks[i].name)
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continue;
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drv_data.src_clocks[i].clk =
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devm_clk_get(&pdev->dev, drv_data.src_clocks[i].name);
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if (IS_ERR(drv_data.src_clocks[i].clk)) {
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dev_err(&pdev->dev, "Unable to get clock %s\n",
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drv_data.src_clocks[i].name);
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return -EPROBE_DEFER;
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}
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}
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/* Enable the always on source */
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clk_prepare_enable(drv_data.src_clocks[PLL0].clk);
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return acpuclk_cortex_init(pdev, &drv_data);
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}
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static struct of_device_id acpuclk_a7_match_table[] = {
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{.compatible = "qcom,acpuclk-a7"},
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{}
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};
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static struct platform_driver acpuclk_a7_driver = {
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.driver = {
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.name = "acpuclk-a7",
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.of_match_table = acpuclk_a7_match_table,
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.owner = THIS_MODULE,
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},
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};
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void msm8610_acpu_init(void)
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{
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drv_data.bus_scale->usecase = bw_level_tbl_8610;
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drv_data.bus_scale->num_usecases = ARRAY_SIZE(bw_level_tbl_8610);
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drv_data.freq_tbl = acpu_freq_tbl_8610;
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}
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static int __init acpuclk_a7_init(void)
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{
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if (cpu_is_msm8610())
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msm8610_acpu_init();
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return platform_driver_probe(&acpuclk_a7_driver, acpuclk_a7_probe);
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}
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device_initcall(acpuclk_a7_init);
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