347 lines
11 KiB
C
347 lines
11 KiB
C
/*
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* Copyright (C) 2009 by Sascha Hauer, Pengutronix
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/list.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/clkdev.h>
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#include <mach/clock.h>
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#include <mach/hardware.h>
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#include <mach/common.h>
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#include <mach/mx25.h>
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#define CRM_BASE MX25_IO_ADDRESS(MX25_CRM_BASE_ADDR)
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#define CCM_MPCTL 0x00
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#define CCM_UPCTL 0x04
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#define CCM_CCTL 0x08
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#define CCM_CGCR0 0x0C
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#define CCM_CGCR1 0x10
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#define CCM_CGCR2 0x14
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#define CCM_PCDR0 0x18
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#define CCM_PCDR1 0x1C
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#define CCM_PCDR2 0x20
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#define CCM_PCDR3 0x24
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#define CCM_RCSR 0x28
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#define CCM_CRDR 0x2C
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#define CCM_DCVR0 0x30
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#define CCM_DCVR1 0x34
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#define CCM_DCVR2 0x38
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#define CCM_DCVR3 0x3c
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#define CCM_LTR0 0x40
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#define CCM_LTR1 0x44
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#define CCM_LTR2 0x48
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#define CCM_LTR3 0x4c
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static unsigned long get_rate_mpll(void)
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{
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ulong mpctl = __raw_readl(CRM_BASE + CCM_MPCTL);
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return mxc_decode_pll(mpctl, 24000000);
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}
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static unsigned long get_rate_upll(void)
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{
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ulong mpctl = __raw_readl(CRM_BASE + CCM_UPCTL);
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return mxc_decode_pll(mpctl, 24000000);
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}
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unsigned long get_rate_arm(struct clk *clk)
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{
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unsigned long cctl = readl(CRM_BASE + CCM_CCTL);
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unsigned long rate = get_rate_mpll();
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if (cctl & (1 << 14))
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rate = (rate * 3) >> 2;
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return rate / ((cctl >> 30) + 1);
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}
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static unsigned long get_rate_ahb(struct clk *clk)
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{
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unsigned long cctl = readl(CRM_BASE + CCM_CCTL);
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return get_rate_arm(NULL) / (((cctl >> 28) & 0x3) + 1);
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}
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static unsigned long get_rate_ipg(struct clk *clk)
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{
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return get_rate_ahb(NULL) >> 1;
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}
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static unsigned long get_rate_per(int per)
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{
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unsigned long ofs = (per & 0x3) * 8;
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unsigned long reg = per & ~0x3;
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unsigned long val = (readl(CRM_BASE + CCM_PCDR0 + reg) >> ofs) & 0x3f;
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unsigned long fref;
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if (readl(CRM_BASE + 0x64) & (1 << per))
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fref = get_rate_upll();
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else
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fref = get_rate_ahb(NULL);
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return fref / (val + 1);
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}
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static unsigned long get_rate_uart(struct clk *clk)
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{
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return get_rate_per(15);
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}
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static unsigned long get_rate_ssi2(struct clk *clk)
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{
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return get_rate_per(14);
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}
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static unsigned long get_rate_ssi1(struct clk *clk)
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{
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return get_rate_per(13);
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}
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static unsigned long get_rate_i2c(struct clk *clk)
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{
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return get_rate_per(6);
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}
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static unsigned long get_rate_nfc(struct clk *clk)
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{
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return get_rate_per(8);
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}
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static unsigned long get_rate_gpt(struct clk *clk)
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{
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return get_rate_per(5);
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}
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static unsigned long get_rate_lcdc(struct clk *clk)
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{
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return get_rate_per(7);
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}
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static unsigned long get_rate_esdhc1(struct clk *clk)
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{
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return get_rate_per(3);
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}
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static unsigned long get_rate_esdhc2(struct clk *clk)
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{
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return get_rate_per(4);
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}
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static unsigned long get_rate_csi(struct clk *clk)
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{
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return get_rate_per(0);
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}
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static unsigned long get_rate_otg(struct clk *clk)
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{
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unsigned long cctl = readl(CRM_BASE + CCM_CCTL);
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unsigned long rate = get_rate_upll();
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return (cctl & (1 << 23)) ? 0 : rate / ((0x3F & (cctl >> 16)) + 1);
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}
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static int clk_cgcr_enable(struct clk *clk)
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{
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u32 reg;
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reg = __raw_readl(clk->enable_reg);
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reg |= 1 << clk->enable_shift;
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__raw_writel(reg, clk->enable_reg);
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return 0;
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}
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static void clk_cgcr_disable(struct clk *clk)
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{
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u32 reg;
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reg = __raw_readl(clk->enable_reg);
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reg &= ~(1 << clk->enable_shift);
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__raw_writel(reg, clk->enable_reg);
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}
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#define DEFINE_CLOCK(name, i, er, es, gr, sr, s) \
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static struct clk name = { \
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.id = i, \
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.enable_reg = CRM_BASE + er, \
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.enable_shift = es, \
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.get_rate = gr, \
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.set_rate = sr, \
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.enable = clk_cgcr_enable, \
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.disable = clk_cgcr_disable, \
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.secondary = s, \
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}
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/*
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* Note: the following IPG clock gating bits are wrongly marked "Reserved" in
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* the i.MX25 Reference Manual Rev 1, table 15-13. The information below is
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* taken from the Freescale released BSP.
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*
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* bit reg offset clock
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*
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* 0 CGCR1 0 AUDMUX
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* 12 CGCR1 12 ESAI
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* 16 CGCR1 16 GPIO1
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* 17 CGCR1 17 GPIO2
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* 18 CGCR1 18 GPIO3
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* 23 CGCR1 23 I2C1
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* 24 CGCR1 24 I2C2
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* 25 CGCR1 25 I2C3
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* 27 CGCR1 27 IOMUXC
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* 28 CGCR1 28 KPP
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* 30 CGCR1 30 OWIRE
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* 36 CGCR2 4 RTIC
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* 51 CGCR2 19 WDOG
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*/
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DEFINE_CLOCK(gpt_clk, 0, CCM_CGCR0, 5, get_rate_gpt, NULL, NULL);
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DEFINE_CLOCK(uart_per_clk, 0, CCM_CGCR0, 15, get_rate_uart, NULL, NULL);
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DEFINE_CLOCK(ssi1_per_clk, 0, CCM_CGCR0, 13, get_rate_ipg, NULL, NULL);
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DEFINE_CLOCK(ssi2_per_clk, 0, CCM_CGCR0, 14, get_rate_ipg, NULL, NULL);
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DEFINE_CLOCK(cspi1_clk, 0, CCM_CGCR1, 5, get_rate_ipg, NULL, NULL);
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DEFINE_CLOCK(cspi2_clk, 0, CCM_CGCR1, 6, get_rate_ipg, NULL, NULL);
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DEFINE_CLOCK(cspi3_clk, 0, CCM_CGCR1, 7, get_rate_ipg, NULL, NULL);
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DEFINE_CLOCK(esdhc1_ahb_clk, 0, CCM_CGCR0, 21, get_rate_esdhc1, NULL, NULL);
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DEFINE_CLOCK(esdhc1_per_clk, 0, CCM_CGCR0, 3, get_rate_esdhc1, NULL,
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&esdhc1_ahb_clk);
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DEFINE_CLOCK(esdhc2_ahb_clk, 0, CCM_CGCR0, 22, get_rate_esdhc2, NULL, NULL);
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DEFINE_CLOCK(esdhc2_per_clk, 0, CCM_CGCR0, 4, get_rate_esdhc2, NULL,
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&esdhc2_ahb_clk);
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DEFINE_CLOCK(sdma_ahb_clk, 0, CCM_CGCR0, 26, NULL, NULL, NULL);
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DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL, NULL, NULL);
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DEFINE_CLOCK(lcdc_ahb_clk, 0, CCM_CGCR0, 24, NULL, NULL, NULL);
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DEFINE_CLOCK(lcdc_per_clk, 0, CCM_CGCR0, 7, NULL, NULL, &lcdc_ahb_clk);
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DEFINE_CLOCK(csi_ahb_clk, 0, CCM_CGCR0, 18, get_rate_csi, NULL, NULL);
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DEFINE_CLOCK(csi_per_clk, 0, CCM_CGCR0, 0, get_rate_csi, NULL, &csi_ahb_clk);
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DEFINE_CLOCK(uart1_clk, 0, CCM_CGCR2, 14, get_rate_uart, NULL, &uart_per_clk);
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DEFINE_CLOCK(uart2_clk, 0, CCM_CGCR2, 15, get_rate_uart, NULL, &uart_per_clk);
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DEFINE_CLOCK(uart3_clk, 0, CCM_CGCR2, 16, get_rate_uart, NULL, &uart_per_clk);
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DEFINE_CLOCK(uart4_clk, 0, CCM_CGCR2, 17, get_rate_uart, NULL, &uart_per_clk);
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DEFINE_CLOCK(uart5_clk, 0, CCM_CGCR2, 18, get_rate_uart, NULL, &uart_per_clk);
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DEFINE_CLOCK(nfc_clk, 0, CCM_CGCR0, 8, get_rate_nfc, NULL, NULL);
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DEFINE_CLOCK(usbotg_clk, 0, CCM_CGCR0, 28, get_rate_otg, NULL, NULL);
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DEFINE_CLOCK(pwm1_clk, 0, CCM_CGCR1, 31, get_rate_ipg, NULL, NULL);
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DEFINE_CLOCK(pwm2_clk, 0, CCM_CGCR2, 0, get_rate_ipg, NULL, NULL);
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DEFINE_CLOCK(pwm3_clk, 0, CCM_CGCR2, 1, get_rate_ipg, NULL, NULL);
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DEFINE_CLOCK(pwm4_clk, 0, CCM_CGCR2, 2, get_rate_ipg, NULL, NULL);
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DEFINE_CLOCK(kpp_clk, 0, CCM_CGCR1, 28, get_rate_ipg, NULL, NULL);
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DEFINE_CLOCK(tsc_clk, 0, CCM_CGCR2, 13, get_rate_ipg, NULL, NULL);
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DEFINE_CLOCK(i2c_clk, 0, CCM_CGCR0, 6, get_rate_i2c, NULL, NULL);
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DEFINE_CLOCK(fec_clk, 0, CCM_CGCR1, 15, get_rate_ipg, NULL, &fec_ahb_clk);
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DEFINE_CLOCK(dryice_clk, 0, CCM_CGCR1, 8, get_rate_ipg, NULL, NULL);
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DEFINE_CLOCK(lcdc_clk, 0, CCM_CGCR1, 29, get_rate_lcdc, NULL, &lcdc_per_clk);
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DEFINE_CLOCK(wdt_clk, 0, CCM_CGCR2, 19, get_rate_ipg, NULL, NULL);
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DEFINE_CLOCK(ssi1_clk, 0, CCM_CGCR2, 11, get_rate_ssi1, NULL, &ssi1_per_clk);
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DEFINE_CLOCK(ssi2_clk, 1, CCM_CGCR2, 12, get_rate_ssi2, NULL, &ssi2_per_clk);
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DEFINE_CLOCK(sdma_clk, 0, CCM_CGCR2, 6, get_rate_ipg, NULL, &sdma_ahb_clk);
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DEFINE_CLOCK(esdhc1_clk, 0, CCM_CGCR1, 13, get_rate_esdhc1, NULL,
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&esdhc1_per_clk);
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DEFINE_CLOCK(esdhc2_clk, 1, CCM_CGCR1, 14, get_rate_esdhc2, NULL,
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&esdhc2_per_clk);
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DEFINE_CLOCK(audmux_clk, 0, CCM_CGCR1, 0, NULL, NULL, NULL);
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DEFINE_CLOCK(csi_clk, 0, CCM_CGCR1, 4, get_rate_csi, NULL, &csi_per_clk);
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DEFINE_CLOCK(can1_clk, 0, CCM_CGCR1, 2, get_rate_ipg, NULL, NULL);
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DEFINE_CLOCK(can2_clk, 1, CCM_CGCR1, 3, get_rate_ipg, NULL, NULL);
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DEFINE_CLOCK(iim_clk, 0, CCM_CGCR1, 26, NULL, NULL, NULL);
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#define _REGISTER_CLOCK(d, n, c) \
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{ \
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.dev_id = d, \
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.con_id = n, \
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.clk = &c, \
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},
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static struct clk_lookup lookups[] = {
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/* i.mx25 has the i.mx21 type uart */
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_REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk)
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_REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk)
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_REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk)
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_REGISTER_CLOCK("imx21-uart.3", NULL, uart4_clk)
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_REGISTER_CLOCK("imx21-uart.4", NULL, uart5_clk)
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_REGISTER_CLOCK("mxc-ehci.0", "usb", usbotg_clk)
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_REGISTER_CLOCK("mxc-ehci.1", "usb", usbotg_clk)
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_REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk)
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_REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk)
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_REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
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/* i.mx25 has the i.mx35 type cspi */
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_REGISTER_CLOCK("imx35-cspi.0", NULL, cspi1_clk)
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_REGISTER_CLOCK("imx35-cspi.1", NULL, cspi2_clk)
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_REGISTER_CLOCK("imx35-cspi.2", NULL, cspi3_clk)
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_REGISTER_CLOCK("mxc_pwm.0", NULL, pwm1_clk)
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_REGISTER_CLOCK("mxc_pwm.1", NULL, pwm2_clk)
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_REGISTER_CLOCK("mxc_pwm.2", NULL, pwm3_clk)
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_REGISTER_CLOCK("mxc_pwm.3", NULL, pwm4_clk)
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_REGISTER_CLOCK("imx-keypad", NULL, kpp_clk)
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_REGISTER_CLOCK("mx25-adc", NULL, tsc_clk)
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_REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
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_REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk)
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_REGISTER_CLOCK("imx-i2c.2", NULL, i2c_clk)
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_REGISTER_CLOCK("imx25-fec.0", NULL, fec_clk)
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_REGISTER_CLOCK("imxdi_rtc.0", NULL, dryice_clk)
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_REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
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_REGISTER_CLOCK("imx2-wdt.0", NULL, wdt_clk)
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_REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
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_REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
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_REGISTER_CLOCK("sdhci-esdhc-imx25.0", NULL, esdhc1_clk)
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_REGISTER_CLOCK("sdhci-esdhc-imx25.1", NULL, esdhc2_clk)
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_REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk)
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_REGISTER_CLOCK(NULL, "audmux", audmux_clk)
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_REGISTER_CLOCK("flexcan.0", NULL, can1_clk)
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_REGISTER_CLOCK("flexcan.1", NULL, can2_clk)
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/* i.mx25 has the i.mx35 type sdma */
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_REGISTER_CLOCK("imx35-sdma", NULL, sdma_clk)
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_REGISTER_CLOCK(NULL, "iim", iim_clk)
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};
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int __init mx25_clocks_init(void)
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{
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clkdev_add_table(lookups, ARRAY_SIZE(lookups));
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/* Turn off all clocks except the ones we need to survive, namely:
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* EMI, GPIO1-3 (CCM_CGCR1[18:16]), GPT1, IOMUXC (CCM_CGCR1[27]), IIM,
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* SCC
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*/
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__raw_writel((1 << 19), CRM_BASE + CCM_CGCR0);
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__raw_writel((0xf << 16) | (3 << 26), CRM_BASE + CCM_CGCR1);
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__raw_writel((1 << 5), CRM_BASE + CCM_CGCR2);
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#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)
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clk_enable(&uart1_clk);
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#endif
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/* Clock source for lcdc and csi is upll */
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__raw_writel(__raw_readl(CRM_BASE+0x64) | (1 << 7) | (1 << 0),
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CRM_BASE + 0x64);
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/* Clock source for gpt is ahb_div */
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__raw_writel(__raw_readl(CRM_BASE+0x64) & ~(1 << 5), CRM_BASE + 0x64);
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clk_enable(&iim_clk);
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imx_print_silicon_rev("i.MX25", mx25_revision());
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clk_disable(&iim_clk);
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mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54);
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return 0;
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}
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