68 lines
3.3 KiB
C
68 lines
3.3 KiB
C
/*****************************************************************************
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* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2, available at
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* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
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*
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* Notwithstanding the above, under no circumstances may you combine this
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* software in any way with any other Broadcom software provided under a
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* license other than the GPL, without Broadcom's express prior written
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* consent.
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*****************************************************************************/
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#ifndef MEMORY_SETTINGS_H
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#define MEMORY_SETTINGS_H
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/* ---- Include Files ---------------------------------------- */
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/* ---- Constants and Types ---------------------------------- */
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/* Memory devices */
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/* NAND Flash timing for 166 MHz setting */
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#define HW_CFG_NAND_tBTA (5 << 16) /* Bus turnaround cycle (n) 0-7 (30 ns) */
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#define HW_CFG_NAND_tWP (4 << 11) /* Write pulse width cycle (n+1) 0-31 (25 ns) */
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#define HW_CFG_NAND_tWR (1 << 9) /* Write recovery cycle (n+1) 0-3 (10 ns) */
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#define HW_CFG_NAND_tAS (0 << 7) /* Write address setup cycle (n+1) 0-3 ( 0 ns) */
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#define HW_CFG_NAND_tOE (3 << 5) /* Output enable delay cycle (n) 0-3 (15 ns) */
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#define HW_CFG_NAND_tRC (7 << 0) /* Read access cycle (n+2) 0-31 (50 ns) */
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#define HW_CFG_NAND_TCR (HW_CFG_NAND_tBTA \
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| HW_CFG_NAND_tWP \
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| HW_CFG_NAND_tWR \
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| HW_CFG_NAND_tAS \
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| HW_CFG_NAND_tOE \
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| HW_CFG_NAND_tRC)
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/* NOR Flash timing for 166 MHz setting */
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#define HW_CFG_NOR_TPRC_TWLC (0 << 19) /* Page read access cycle / Burst write latency (n+2 / n+1) (max 25ns) */
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#define HW_CFG_NOR_TBTA (0 << 16) /* Bus turnaround cycle (n) (DNA) */
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#define HW_CFG_NOR_TWP (6 << 11) /* Write pulse width cycle (n+1) (35ns) */
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#define HW_CFG_NOR_TWR (0 << 9) /* Write recovery cycle (n+1) (0ns) */
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#define HW_CFG_NOR_TAS (0 << 7) /* Write address setup cycle (n+1) (0ns) */
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#define HW_CFG_NOR_TOE (0 << 5) /* Output enable delay cycle (n) (max 25ns) */
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#define HW_CFG_NOR_TRC_TLC (0x10 << 0) /* Read access cycle / Burst read latency (n+2 / n+1) (100ns) */
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#define HW_CFG_FLASH0_TCR (HW_CFG_NOR_TPRC_TWLC \
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| HW_CFG_NOR_TBTA \
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| HW_CFG_NOR_TWP \
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| HW_CFG_NOR_TWR \
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| HW_CFG_NOR_TAS \
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| HW_CFG_NOR_TOE \
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| HW_CFG_NOR_TRC_TLC)
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#define HW_CFG_FLASH1_TCR HW_CFG_FLASH0_TCR
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#define HW_CFG_FLASH2_TCR HW_CFG_FLASH0_TCR
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/* SDRAM Settings */
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/* #define HW_CFG_SDRAM_CAS_LATENCY 5 Default 5, Values [3..6] */
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/* #define HW_CFG_SDRAM_CHIP_SELECT_CNT 1 Default 1, Vaules [1..2] */
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/* #define HW_CFG_SDRAM_SPEED_GRADE 667 Default 667, Values [400,533,667,800] */
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/* #define HW_CFG_SDRAM_WIDTH_BITS 16 Default 16, Vaules [8,16] */
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#define HW_CFG_SDRAM_SIZE_BYTES 0x10000000 /* Total memory, not per device size */
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/* ---- Variable Externs ------------------------------------- */
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/* ---- Function Prototypes ---------------------------------- */
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#endif /* MEMORY_SETTINGS_H */
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