146 lines
5.3 KiB
C
146 lines
5.3 KiB
C
/*****************************************************************************
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* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2, available at
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* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
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*
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* Notwithstanding the above, under no circumstances may you combine this
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* software in any way with any other Broadcom software provided under a
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* license other than the GPL, without Broadcom's express prior written
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* consent.
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*****************************************************************************/
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/****************************************************************************/
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/**
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* @file dmacHw_priv.h
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*
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* @brief Private Definitions for low level DMA driver
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*
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*/
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/****************************************************************************/
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#ifndef _DMACHW_PRIV_H
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#define _DMACHW_PRIV_H
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#include <csp/stdint.h>
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/* Data type for DMA Link List Item */
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typedef struct {
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uint32_t sar; /* Source Address Register.
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Address must be aligned to CTLx.SRC_TR_WIDTH. */
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uint32_t dar; /* Destination Address Register.
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Address must be aligned to CTLx.DST_TR_WIDTH. */
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uint32_t llpPhy; /* LLP contains the physical address of the next descriptor for block chaining using linked lists.
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Address MUST be aligned to a 32-bit boundary. */
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dmacHw_REG64_t ctl; /* Control Register. 64 bits */
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uint32_t sstat; /* Source Status Register */
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uint32_t dstat; /* Destination Status Register */
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uint32_t devCtl; /* Device specific control information */
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uint32_t llp; /* LLP contains the virtual address of the next descriptor for block chaining using linked lists. */
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} dmacHw_DESC_t;
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/*
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* Descriptor ring pointers
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*/
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typedef struct {
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int num; /* Number of link items */
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dmacHw_DESC_t *pHead; /* Head of descriptor ring (for writing) */
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dmacHw_DESC_t *pTail; /* Tail of descriptor ring (for reading) */
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dmacHw_DESC_t *pProg; /* Descriptor to program the channel (for programming the channel register) */
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dmacHw_DESC_t *pEnd; /* End of current descriptor chain */
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dmacHw_DESC_t *pFree; /* Descriptor to free memory (freeing dynamic memory) */
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uint32_t virt2PhyOffset; /* Virtual to physical address offset for the descriptor ring */
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} dmacHw_DESC_RING_t;
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/*
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* DMA channel control block
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*/
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typedef struct {
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uint32_t module; /* DMA controller module (0-1) */
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uint32_t channel; /* DMA channel (0-7) */
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volatile uint32_t varDataStarted; /* Flag indicating variable data channel is enabled */
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volatile uint32_t descUpdated; /* Flag to indicate descriptor update is complete */
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void *userData; /* Channel specifc user data */
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} dmacHw_CBLK_t;
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#define dmacHw_ASSERT(a) if (!(a)) while (1)
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#define dmacHw_MAX_CHANNEL_COUNT 16
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#define dmacHw_FREE_USER_MEMORY 0xFFFFFFFF
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#define dmacHw_DESC_FREE dmacHw_REG_CTL_DONE
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#define dmacHw_DESC_INIT ((dmacHw_DESC_t *) 0xFFFFFFFF)
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#define dmacHw_MAX_BLOCKSIZE 4064
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#define dmacHw_GET_DESC_RING(addr) (dmacHw_DESC_RING_t *)(addr)
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#define dmacHw_ADDRESS_MASK(byte) ((byte) - 1)
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#define dmacHw_NEXT_DESC(rp, dp) ((rp)->dp = (dmacHw_DESC_t *)(rp)->dp->llp)
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#define dmacHw_HANDLE_TO_CBLK(handle) ((dmacHw_CBLK_t *) (handle))
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#define dmacHw_CBLK_TO_HANDLE(cblkp) ((dmacHw_HANDLE_t) (cblkp))
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#define dmacHw_DST_IS_MEMORY(tt) (((tt) == dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM) || ((tt) == dmacHw_TRANSFER_TYPE_MEM_TO_MEM)) ? 1 : 0
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/****************************************************************************/
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/**
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* @brief Get next available transaction width
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*
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*
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* @return On success : Next available transaction width
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* On failure : dmacHw_TRANSACTION_WIDTH_8
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*
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* @note
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* None
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*/
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/****************************************************************************/
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static inline dmacHw_TRANSACTION_WIDTH_e dmacHw_GetNextTrWidth(dmacHw_TRANSACTION_WIDTH_e tw /* [ IN ] Current transaction width */
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) {
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if (tw & dmacHw_REG_CTL_SRC_TR_WIDTH_MASK) {
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return ((tw >> dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT) -
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1) << dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT;
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} else if (tw & dmacHw_REG_CTL_DST_TR_WIDTH_MASK) {
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return ((tw >> dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT) -
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1) << dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT;
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}
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/* Default return */
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return dmacHw_SRC_TRANSACTION_WIDTH_8;
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}
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/****************************************************************************/
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/**
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* @brief Get number of bytes per transaction
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*
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* @return Number of bytes per transaction
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*
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*
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* @note
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* None
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*/
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/****************************************************************************/
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static inline int dmacHw_GetTrWidthInBytes(dmacHw_TRANSACTION_WIDTH_e tw /* [ IN ] Transaction width */
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) {
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int width = 1;
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switch (tw) {
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case dmacHw_SRC_TRANSACTION_WIDTH_8:
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width = 1;
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break;
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case dmacHw_SRC_TRANSACTION_WIDTH_16:
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case dmacHw_DST_TRANSACTION_WIDTH_16:
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width = 2;
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break;
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case dmacHw_SRC_TRANSACTION_WIDTH_32:
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case dmacHw_DST_TRANSACTION_WIDTH_32:
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width = 4;
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break;
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case dmacHw_SRC_TRANSACTION_WIDTH_64:
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case dmacHw_DST_TRANSACTION_WIDTH_64:
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width = 8;
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break;
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default:
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dmacHw_ASSERT(0);
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}
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/* Default transaction width */
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return width;
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}
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#endif /* _DMACHW_PRIV_H */
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