310 lines
9.8 KiB
Plaintext
310 lines
9.8 KiB
Plaintext
Driver name: Qualcomm FSM9xxx Ethernet Driver
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Supported hardware: FSM9xxx Ethernet Controller
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Maintainer(s):
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Author(s):
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Introduction:
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=============
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The FSM9xxx Ethernet controller is register based with separate TX and RX DMA
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engines supporting scatter/gather and support 1EEE-1588 timestamping.
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MII, RevMII and RgMII interfaces are support. RgMII support 1G.
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The driver supports gather but not scatter, uses the controller DMA engines,
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and timestamping.
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Hardware description:
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=====================
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The Ethernet Controller is a memory mapped register device with two
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internal DMA engines for TX and RX path processing using separate
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buffer-descriptors (BD) allocated from non-cached main memory for the TX
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and RX paths. These BDs support scatter-gather but are only used to
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transfer single max sized Ethernet frames. The BDs are sequentially
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accessed as a ring, with an end-of-ring bit set in the last BD. Ownership
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bits control access by hardware and software to individual BDs.
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An additional 4 words of space can be configured and is allocated between
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each BD to store additional information about the sk_buff associated with it.
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The driver software uses 2 ring structures and local functions to manage
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them to keep in sync with the hardware the BDs . The number of BDs is
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determined from the space allocated for them (PAGE_SIZE). The ratio of RX
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to TX BD is set by a #define.
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Interrupts are used to service and replenish pre-allocated sk_buff for each
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RX BD. TX frames are allocated to a TX BD and transmitted frames are
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freed within the xmit() invoked to send the frame. No TX interrupts are
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processed since sk_buffs are freed in the xmit().
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Three PHY interfaces are supported: MII, RevMII and RgMII. The selected
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interface is determined from the resource structure (to be completed) and
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programmed into a register prior to resetting the Ethernet controller.
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Separate PLLs are managed to provide MAC/PHY clocks in RevMii and RgMii
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modes, and a 25mHz clock timestamping.
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Software description
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====================
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Structures
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struct qfec_buf_desc {
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uint32_t status;
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uint32_t ctl;
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void *p_buf;
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void *next;
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};
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struct buf_desc {
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struct qfec_buf_desc desc; /* must be first */
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struct sk_buff *skb;
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void *buf_virt_addr;
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void *buf_phys_addr;
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uint32_t last_bd_flag;
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};
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struct ring {
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int head;
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int tail;
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int n_free;
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int len;
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};
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struct qfec_priv {
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struct net_device *net_dev;
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struct net_device_stats stats; /* req statistics */
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struct device dev;
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spinlock_t hw_lock;
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unsigned int state; /* driver state */
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void *bd_base; /* addr buf-desc */
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dma_addr_t tbd_dma; /* dma/phy-addr buf-desc */
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dma_addr_t rbd_dma; /* dma/phy-addr buf-desc */
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struct resource *mac_res;
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void *mac_base; /* mac (virt) base address */
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struct resource *clk_res;
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void *clk_base; /* clk (virt) base address */
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unsigned int n_tbd; /* # of TX buf-desc */
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struct ring ring_tbd; /* TX ring */
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struct buf_desc *p_tbd; /* # TX buf-desc */
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unsigned int n_rbd; /* # of RX buf-desc */
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struct ring ring_rbd; /* RX ring */
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struct buf_desc *p_rbd; /* # RX buf-desc */
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unsigned long cntr[cntr_last]; /* activity counters */
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struct mii_if_info mii;
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int mdio_clk; /* phy mdio clock rate */
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int phy_id; /* default PHY addr (0) */
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struct timer_list phy_tmr; /* monitor PHY state */
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};
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Initialization is divided between probe() and open() such that the
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net_device is allocated, the address space is mapped for register access,
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and procfs files created in probe(). BD memory is allocated and
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initialized along with interrupts and timers in open(). BD is not
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de-allocated in close() allowing it to be debugged after the interface is
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ifconfig down'd. This approach is intended to aid with debugging by
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allowing configuring the interface down and up may clear some early usage
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problems
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Phy link state changes are monitored using a timer using some existing
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functions from the mii library, but also with local functions intended to
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support RGMII in the future.
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A variety of information is accessible through procFs. Counters are used
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to track various driver events, these include abnormal and error
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interrupts. Hardware counters of various frame statistics (e.g. types and
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sizes of TX and RX frames) are available. Hardware registers and up to the
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50 TX and RX BDs can be can be displayed. A table of procfs filenames and
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functions are used to create and delete the procfs entries as needed.
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Probe()
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Allocate and initialize the net_device structure with resource information
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specifying the Ethernet controller, clock control and MAC address memory
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regions. Set netdev_ops to a statically defined sub-structure supporting
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the device.
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Open()
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Use qfec_mem_alloc() to allocate space for the buffer-descriptors (BD).
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TX BDs are initialized by clearing the ownership bit of each. Each RX BD
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is initialized using qfec_rbd_init(). Qfec_rbd_init() pre-allocates an
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sk_buff, saving the addresses of both the sk_buff and its data buffer in the
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additional BD space, setting the BD buf pointer to the physical address of
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the sk_buff data, and finally setting the ownership bit.
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Once the BDs are initialized, interface selected register is set to the
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appropriate PHY interface configuration, and the Ethernet controller is
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reset and its registers initialized, including the starting addresses of
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the TX and RX BDs.
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The PHY monitor state is initialized and the timer initialized and started.
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Finally, the interrupt for the Ethernet controller is initialized.
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Note - Interrupts from both from the external PHY and internal RevMii
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PHY, are available, but neither is used in preference to the
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timer.
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Interrupt Processing
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Besides recognizing abnormal error interrupts, RX, TX and GMAC interrupts
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are recognized, although TX and GMAC interrupts are ignored but cleared and
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counted. (The gmac interrupt can be ignored but must be disabled).
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RX interrupts invoke a handler to process the received frame, send it
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to the stack and re-allocate a replacement sk_bufff for the buffer-
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descriptor.
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Receive Processing
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The RX buffer descriptors are initialized by _open() using qfec_rbd_init()
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which pre-allocated an sk_buff, saving its address and the physical address
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of its data in the additional BD space, as well as writing the physical
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address to the BD pbuf entry read by HW. The size of the buffer and
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other control information are written to the BD, as well as setting the
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ownership bit.
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A received frame generates an interrupt invoking qfec_rx_int(). It
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repeatedly checks the ownership the next available BD, and passing the
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sk_buff containing the received frame to the stack via netif_rx().
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Once all received frames are processed, it repeatedly calls qfec_rbd_init()
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to allocate a new sk_buff with each available BD.
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Transmit Processing
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Frames are transmitted through the start_xmit callback function.
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qfec_tx_replenish() is immediately called to free sk_buffs from BD
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that have been transmitted, before checking is a BD is available.
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The sk_buff address is stored in the additional BD space and the
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physical address of its data is store in the pbuf BD entry used
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by the HW. The TX poll-demand register is accessed, causing the
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HW to recheck the current BD and process it.
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While the TX interrupt could be processed to free sk_buffs as BD
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are processed, they are ignored since the sk_buffs will be freed
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with each call to _xmit().
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procfs
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debug files are available to display the controller registers,
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frame counters from the controller, driver activity counters, and
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the first 50 entries of the RX and TX buffer descriptors.
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Callbacks
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In addition to the functions described above, the following functions
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are used to support their correspondingly named device operations:
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qfec_stop
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qfec_do_ioctl
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qfec_tx_timeout
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qfec_set_mac_address
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qfec_get_stats
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qfec_set_config
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eth_change_mtu
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eth_validate_addr
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Power Management
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================
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None
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Interface:
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==========
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- Module-init/exit
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- standard network interface functions
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Module parameters:
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==================
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static struct resource qfec_resources [] = {
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[0] = {
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.start = QFEC_MAC_BASE,
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.end = QFEC_MAC_BASE + QFEC_MAC_SIZE,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = QFEC_MAC_IRQ,
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.end = QFEC_MAC_IRQ,
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.flags = IORESOURCE_IRQ,
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},
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[2] = {
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.start = QFEC_CLK_BASE,
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.end = QFEC_CLK_BASE + QFEC_CLK_SIZE,
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.flags = IORESOURCE_IO,
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},
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[3] = {
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.start = QFEC_MAC_FUSE_BASE,
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.end = QFEC_MAC_FUSE_BASE + QFEC_MAC_FUSE_SIZE,
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.flags = IORESOURCE_DMA,
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},
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};
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static struct platform_device qfec_device = {
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.name = "qfec",
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.id = 0,
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.num_resources = ARRAY_SIZE(qfec_resources),
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.resource = qfec_resources,
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};
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Resource entries exist for three address regions and one interrupt. The
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interrupt is identified as IORESOURCE_IRQ, the controller registers as
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OPRESOURCE_MEM, the clock control registers as IORESOURCE_IO, and the
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MAC address fuses as IORESOURCE_DMA.
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Dependencies:
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=============
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None
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User space utilities:
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=====================
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See procfs descriptions
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Known issues:
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=============
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- replace procfs w/ debugfs
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To do:
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======
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- specify interface (MII/RevMII/RgMii) in resource structure
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- RevMii support untested
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- RgMii (10/100/1000)
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- generic timestamp support
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