318 lines
9.4 KiB
C
318 lines
9.4 KiB
C
/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of The Linux Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <debug.h>
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#include <reg.h>
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#include <spmi.h>
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#include <platform/iomap.h>
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#include <platform/irqs.h>
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#include <platform/interrupts.h>
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static uint32_t pmic_arb_chnl_num;
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static uint32_t pmic_arb_owner_id;
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static uint8_t pmic_irq_perph_id;
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static spmi_callback callback;
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/* Function to initialize SPMI controller.
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* chnl_num : Channel number to be used by this EE.
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*/
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void spmi_init(uint32_t chnl_num, uint32_t owner_id)
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{
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/* Initialize PMIC Arbiter Channel Number */
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pmic_arb_chnl_num = chnl_num;
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pmic_arb_owner_id = owner_id;
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}
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static void write_wdata_from_array(uint8_t *array,
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uint8_t reg_num,
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uint8_t array_size,
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uint8_t* bytes_written)
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{
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uint32_t shift_value[] = {0, 8, 16, 24};
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int i;
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int j;
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uint32_t val = 0;
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/* Write to WDATA */
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for (i = 0; (*bytes_written < array_size) && (i < 4); i++)
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{
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val |= (uint32_t)(array[*bytes_written]) << shift_value[i];
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(*bytes_written)++;
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}
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writel(val, PMIC_ARB_CHNLn_WDATA(pmic_arb_chnl_num, reg_num));
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}
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/* Initiate a write cmd by writing to cmd register.
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* Commands are written according to cmd parameters
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* cmd->opcode : SPMI opcode for the command
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* cmd->priority : Priority of the command
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* High priority : 1
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* Low Priority : 0
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* cmd->address : SPMI Peripheral Address.
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* cmd->offset : Offset Address for the command.
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* cmd->bytecnt : Number of bytes to be written.
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*
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* param is the parameter to the command
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* param->buffer : Value to be written
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* param->size : Size of the buffer.
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*
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* return value : 0 if success, the error bit set on error
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*/
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unsigned int pmic_arb_write_cmd(struct pmic_arb_cmd *cmd,
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struct pmic_arb_param *param)
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{
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uint32_t bytes_written = 0;
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uint32_t error;
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uint32_t val = 0;
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/* Disable IRQ mode for the current channel*/
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writel(0x0, PMIC_ARB_CHNLn_CONFIG(pmic_arb_chnl_num));
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/* Write parameters for the cmd */
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if (cmd == NULL)
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{
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dprintf(CRITICAL,"PMIC arbiter error, no command provided\n");
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return 1;
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}
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/* Write the data bytes according to the param->size
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* Can write upto 8 bytes.
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*/
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/* Write first 4 bytes to WDATA0 */
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write_wdata_from_array(param->buffer, 0, param->size, &bytes_written);
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if (bytes_written < param->size)
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{
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/* Write next 4 bytes to WDATA1 */
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write_wdata_from_array(param->buffer, 1, param->size, &bytes_written);
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}
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/* Fill in the byte count for the command
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* Note: Byte count is one less than the number of bytes transferred.
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*/
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cmd->byte_cnt = param->size - 1;
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/* Fill in the Write cmd opcode. */
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cmd->opcode = SPMI_CMD_EXT_REG_WRTIE_LONG;
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/* Write the command */
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val = 0;
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val |= ((uint32_t)(cmd->opcode) << PMIC_ARB_CMD_OPCODE_SHIFT);
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val |= ((uint32_t)(cmd->priority) << PMIC_ARB_CMD_PRIORITY_SHIFT);
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val |= ((uint32_t)(cmd->slave_id) << PMIC_ARB_CMD_SLAVE_ID_SHIFT);
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val |= ((uint32_t)(cmd->address) << PMIC_ARB_CMD_ADDR_SHIFT);
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val |= ((uint32_t)(cmd->offset) << PMIC_ARB_CMD_ADDR_OFFSET_SHIFT);
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val |= ((uint32_t)(cmd->byte_cnt));
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writel(val, PMIC_ARB_CHNLn_CMD0(pmic_arb_chnl_num));
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/* Wait till CMD DONE status */
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while (!(val = readl(PMIC_ARB_CHNLn_STATUS(pmic_arb_chnl_num))));
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/* Check for errors */
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error = val ^ (1 << PMIC_ARB_CMD_DONE);
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if (error)
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{
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dprintf(CRITICAL, "SPMI write command failure: \
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cmd_id = %u, error = %u\n", cmd->opcode, error);
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return error;
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}
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else
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return 0;
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}
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static void read_rdata_into_array(uint8_t *array,
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uint8_t reg_num,
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uint8_t array_size,
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uint8_t* bytes_read)
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{
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uint32_t val = 0;
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uint32_t mask_value[] = {0xFF, 0xFF00, 0xFF0000, 0xFF000000};
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uint8_t shift_value[] = {0, 8, 16, 24};
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int i;
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val = readl(PMIC_ARB_CHNLn_RDATA(pmic_arb_chnl_num, reg_num));
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/* Read at most 4 bytes */
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for (i = 0; (i < 4) && (*bytes_read < array_size); i++)
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{
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array[*bytes_read] = (val & mask_value[i]) >> shift_value[i];
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(*bytes_read)++;
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}
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}
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/* Initiate a read cmd by writing to cmd register.
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* Commands are written according to cmd parameters
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* cmd->opcode : SPMI opcode for the command
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* cmd->priority : Priority of the command
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* High priority : 1
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* Low Priority : 0
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* cmd->address : SPMI Peripheral Address.
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* cmd->offset : Offset Address for the command.
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* cmd->bytecnt : Number of bytes to be read.
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*
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* param is the buffer to the save command data.
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* param->buffer : Buffer to store the bytes returned.
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* param->size : Size of the buffer.
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*
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* return value : 0 if success, the error bit set on error
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*/
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unsigned int pmic_arb_read_cmd(struct pmic_arb_cmd *cmd,
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struct pmic_arb_param *param)
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{
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uint32_t val = 0;
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uint32_t error;
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uint32_t addr;
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uint8_t bytes_read = 0;
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/* Disable IRQ mode for the current channel*/
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writel(0x0, PMIC_ARB_CHNLn_CONFIG(pmic_arb_chnl_num));
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/* Fill in the byte count for the command
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* Note: Byte count is one less than the number of bytes transferred.
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*/
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cmd->byte_cnt = param->size - 1;
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/* Fill in the Write cmd opcode. */
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cmd->opcode = SPMI_CMD_EXT_REG_READ_LONG;
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val |= ((uint32_t)(cmd->opcode) << PMIC_ARB_CMD_OPCODE_SHIFT);
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val |= ((uint32_t)(cmd->priority) << PMIC_ARB_CMD_PRIORITY_SHIFT);
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val |= ((uint32_t)(cmd->slave_id) << PMIC_ARB_CMD_SLAVE_ID_SHIFT);
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val |= ((uint32_t)(cmd->address) << PMIC_ARB_CMD_ADDR_SHIFT);
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val |= ((uint32_t)(cmd->offset) << PMIC_ARB_CMD_ADDR_OFFSET_SHIFT);
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val |= ((uint32_t)(cmd->byte_cnt));
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writel(val, PMIC_ARB_CHNLn_CMD0(pmic_arb_chnl_num));
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/* Wait till CMD DONE status */
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while (!(val = readl(PMIC_ARB_CHNLn_STATUS(pmic_arb_chnl_num))));
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/* Check for errors */
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error = val ^ (1 << PMIC_ARB_CMD_DONE);
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if (error)
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{
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dprintf(CRITICAL, "SPMI read command failure: \
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cmd_id = %u, error = %u\n", cmd->opcode, error);
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return error;
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}
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/* Read the RDATA0 */
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read_rdata_into_array(param->buffer, 0, param->size , &bytes_read);
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if (bytes_read < param->size)
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{
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/* Read the RDATA1 */
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read_rdata_into_array(param->buffer, 1, param->size , &bytes_read);
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}
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if (bytes_read < param->size)
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{
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/* Read the RDATA2 */
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read_rdata_into_array(param->buffer, 2, param->size , &bytes_read);
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}
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return 0;
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}
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/* Funtion to determine if the peripheral that caused the interrupt
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* is of interest.
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* Also handles callback function and interrupt clearing if the
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* correct interrupt is fired.
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* periph_acc_irq: SPMI_PIC_OWNERm_ACC_STATUSn register id.
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* status: Bits of the periph_acc_irq.
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* return 1 if the peripheral is of interest,
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* 0 otherwise.
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*/
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int spmi_acc_irq(uint32_t periph_acc_irq, uint32_t status)
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{
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uint8_t reg_id;
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uint8_t offset;
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/* Narrow down the correct register for the peripheral*/
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reg_id = pmic_irq_perph_id / 32;
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if (periph_acc_irq * 8 != reg_id)
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return 0;
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/* Narrow down the correct interrupt within the register */
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offset = pmic_irq_perph_id & 31;
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if ((status & offset))
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{
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/* Clear the interrupt */
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writel(offset ^ status, SPMI_PIC_IRQ_CLEARn(reg_id));
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/* Confirm that the interrupt has been cleared */
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while(readl(SPMI_PIC_IRQ_STATUSn(reg_id)) & offset);
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/* Call the callback */
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callback();
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return 1;
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}
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else
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return 0;
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}
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void spmi_irq()
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{
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int i;
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uint32_t status;
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/* Go through the Peripheral list to figure out the periperal
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* that caused the interrupt
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*/
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for (i = 0; i < 8; i++)
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{
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status = readl(SPMI_PIC_OWNERm_ACC_STATUSn(pmic_arb_owner_id, i));
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if (status)
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if (!spmi_acc_irq(i, status))
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/* Not the correct interrupt, continue to wait */
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return;
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}
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mask_interrupt(EE0_KRAIT_HLOS_SPMI_PERIPH_IRQ);
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}
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/* Enable interrupts on a particular peripheral: periph_id */
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void spmi_enable_periph_interrupts(uint8_t periph_id)
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{
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pmic_irq_perph_id = periph_id;
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register_int_handler(EE0_KRAIT_HLOS_SPMI_PERIPH_IRQ , spmi_irq, 0);
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unmask_interrupt(EE0_KRAIT_HLOS_SPMI_PERIPH_IRQ);
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}
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void spmi_uninit()
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{
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mask_interrupt(EE0_KRAIT_HLOS_SPMI_PERIPH_IRQ);
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}
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