346 lines
11 KiB
C
346 lines
11 KiB
C
/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of The Linux Foundation nor
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* the names of its contributors may be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <mdp5.h>
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#include <debug.h>
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#include <reg.h>
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#include <target/display.h>
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#include <platform/timer.h>
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#include <platform/iomap.h>
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#include <dev/lcdc.h>
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#include <dev/fbcon.h>
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#include <bits.h>
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#include <msm_panel.h>
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#include <mipi_dsi.h>
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#include <err.h>
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#include <clock.h>
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#include <mdp5.h>
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#include <scm.h>
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int restore_secure_cfg(uint32_t id);
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static int mdp_rev;
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void mdp_set_revision(int rev)
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{
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mdp_rev = rev;
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}
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int mdp_get_revision()
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{
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return mdp_rev;
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}
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uint32_t mdss_mdp_intf_offset()
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{
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uint32_t mdss_mdp_intf_off;
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uint32_t mdss_mdp_rev = readl(MDP_HW_REV);
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if (mdss_mdp_rev > MDSS_MDP_HW_REV_100)
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mdss_mdp_intf_off = 0;
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else
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mdss_mdp_intf_off = 0xEC00;
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return mdss_mdp_intf_off;
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}
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void mdp_clk_gating_ctrl(void)
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{
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writel(0x40000000, MDP_CLK_CTRL0);
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udelay(20);
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writel(0x40000040, MDP_CLK_CTRL0);
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writel(0x40000000, MDP_CLK_CTRL1);
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writel(0x00400000, MDP_CLK_CTRL3);
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udelay(20);
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writel(0x00404000, MDP_CLK_CTRL3);
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writel(0x40000000, MDP_CLK_CTRL4);
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}
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int mdp_dsi_video_config(struct msm_panel_info *pinfo,
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struct fbcon_config *fb)
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{
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int ret = NO_ERROR;
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uint32_t hsync_period, vsync_period;
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uint32_t hsync_start_x, hsync_end_x;
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uint32_t display_hctl, active_hctl, hsync_ctl, display_vstart, display_vend;
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struct lcdc_panel_info *lcdc = NULL;
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unsigned mdp_rgb_size;
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int access_secure = 0;
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uint32_t mdss_mdp_intf_off = 0;
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if (pinfo == NULL)
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return ERR_INVALID_ARGS;
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lcdc = &(pinfo->lcdc);
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if (lcdc == NULL)
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return ERR_INVALID_ARGS;
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hsync_period = lcdc->h_pulse_width +
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lcdc->h_back_porch +
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pinfo->xres + lcdc->xres_pad + lcdc->h_front_porch;
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vsync_period = (lcdc->v_pulse_width +
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lcdc->v_back_porch +
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pinfo->yres + lcdc->yres_pad +
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lcdc->v_front_porch);
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hsync_start_x =
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lcdc->h_pulse_width +
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lcdc->h_back_porch;
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hsync_end_x =
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hsync_period - lcdc->h_front_porch - 1;
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display_vstart = (lcdc->v_pulse_width +
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lcdc->v_back_porch)
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* hsync_period + lcdc->hsync_skew;
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display_vend = ((vsync_period - lcdc->v_front_porch) * hsync_period)
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+lcdc->hsync_skew - 1;
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hsync_ctl = (hsync_period << 16) | lcdc->h_pulse_width;
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display_hctl = (hsync_end_x << 16) | hsync_start_x;
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mdss_mdp_intf_off = mdss_mdp_intf_offset();
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/* write active region size*/
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mdp_rgb_size = (fb->height << 16) + fb->width;
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access_secure = restore_secure_cfg(SECURE_DEVICE_MDSS);
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mdp_clk_gating_ctrl();
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/* Ignore TZ return value till it's fixed */
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if (!access_secure || 1) {
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/* Force VBIF Clocks on */
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writel(0x1, VBIF_VBIF_DDR_FORCE_CLK_ON);
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if (readl(MDP_HW_REV) == MDSS_MDP_HW_REV_100) {
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/* Configure DDR burst length */
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writel(0x00000707, VBIF_VBIF_DDR_OUT_MAX_BURST);
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writel(0x00000030, VBIF_VBIF_DDR_ARB_CTRL );
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writel(0x00000001, VBIF_VBIF_DDR_RND_RBN_QOS_ARB);
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writel(0x00000FFF, VBIF_VBIF_DDR_OUT_AOOO_AXI_EN);
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writel(0x0FFF0FFF, VBIF_VBIF_DDR_OUT_AX_AOOO);
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writel(0x22222222, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0);
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writel(0x00002222, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1);
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}
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}
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/* Allocate SMP blocks */
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writel(0x00101010, MMSS_MDP_SMP_ALLOC_W_0);
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writel(0x00000010, MMSS_MDP_SMP_ALLOC_W_1);
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writel(0x00101010, MMSS_MDP_SMP_ALLOC_R_0);
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writel(0x00000010, MMSS_MDP_SMP_ALLOC_R_1);
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writel(hsync_ctl, MDP_INTF_1_HSYNC_CTL + mdss_mdp_intf_off);
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writel(vsync_period*hsync_period, MDP_INTF_1_VSYNC_PERIOD_F0 +
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mdss_mdp_intf_off);
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writel(0x00, MDP_INTF_1_VSYNC_PERIOD_F1 + mdss_mdp_intf_off);
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writel(lcdc->v_pulse_width*hsync_period,
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MDP_INTF_1_VSYNC_PULSE_WIDTH_F0 +
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mdss_mdp_intf_off);
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writel(0x00, MDP_INTF_1_VSYNC_PULSE_WIDTH_F1 + mdss_mdp_intf_off);
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writel(display_hctl, MDP_INTF_1_DISPLAY_HCTL + mdss_mdp_intf_off);
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writel(display_vstart, MDP_INTF_1_DISPLAY_V_START_F0 +
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mdss_mdp_intf_off);
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writel(0x00, MDP_INTF_1_DISPLAY_V_START_F1 + mdss_mdp_intf_off);
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writel(display_vend, MDP_INTF_1_DISPLAY_V_END_F0 +
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mdss_mdp_intf_off);
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writel(0x00, MDP_INTF_1_DISPLAY_V_END_F1 + mdss_mdp_intf_off);
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writel(0x00, MDP_INTF_1_ACTIVE_HCTL + mdss_mdp_intf_off);
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writel(0x00, MDP_INTF_1_ACTIVE_V_START_F0 + mdss_mdp_intf_off);
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writel(0x00, MDP_INTF_1_ACTIVE_V_START_F1 + mdss_mdp_intf_off);
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writel(0x00, MDP_INTF_1_ACTIVE_V_END_F0 + mdss_mdp_intf_off);
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writel(0x00, MDP_INTF_1_ACTIVE_V_END_F1 + mdss_mdp_intf_off);
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writel(0xFF, MDP_INTF_1_UNDERFFLOW_COLOR + mdss_mdp_intf_off);
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writel(fb->base, MDP_VP_0_RGB_0_SSPP_SRC0_ADDR);
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writel((fb->stride * fb->bpp/8),MDP_VP_0_RGB_0_SSPP_SRC_YSTRIDE);
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writel(mdp_rgb_size, MDP_VP_0_RGB_0_SSPP_SRC_IMG_SIZE);
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writel(mdp_rgb_size, MDP_VP_0_RGB_0_SSPP_SRC_SIZE);
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writel(mdp_rgb_size, MDP_VP_0_RGB_0_SSPP_SRC_OUT_SIZE);
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writel(0x00, MDP_VP_0_RGB_0_SSPP_SRC_XY);
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writel(0x00, MDP_VP_0_RGB_0_SSPP_OUT_XY);
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/* Tight Packing 3bpp 0-Alpha 8-bit R B G */
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writel(0x0002243F, MDP_VP_0_RGB_0_SSPP_SRC_FORMAT);
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writel(0x00020001, MDP_VP_0_RGB_0_SSPP_SRC_UNPACK_PATTERN);
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writel(0x00, MDP_VP_0_RGB_0_SSPP_SRC_OP_MODE);
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writel(mdp_rgb_size,MDP_VP_0_LAYER_0_OUT_SIZE);
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writel(0x00, MDP_VP_0_LAYER_0_OP_MODE);
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writel(0x100, MDP_VP_0_LAYER_0_BLEND_OP);
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writel(0xFF, MDP_VP_0_LAYER_0_BLEND0_FG_ALPHA);
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writel(0x100, MDP_VP_0_LAYER_1_BLEND_OP);
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writel(0xFF, MDP_VP_0_LAYER_1_BLEND0_FG_ALPHA);
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writel(0x100, MDP_VP_0_LAYER_2_BLEND_OP);
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writel(0xFF, MDP_VP_0_LAYER_2_BLEND0_FG_ALPHA);
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writel(0x100, MDP_VP_0_LAYER_3_BLEND_OP);
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writel(0xFF, MDP_VP_0_LAYER_3_BLEND0_FG_ALPHA);
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/* Baselayer for layer mixer 0 */
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writel(0x010000200, MDP_CTL_0_LAYER_0);
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writel(0x1F20, MDP_CTL_0_TOP);
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writel(0x213F, MDP_INTF_1_PANEL_FORMAT + mdss_mdp_intf_off);
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writel(0x0100, MDP_DISP_INTF_SEL);
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writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL);
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writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START);
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writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START);
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return 0;
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}
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int mdp_dsi_cmd_config(struct msm_panel_info *pinfo,
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struct fbcon_config *fb)
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{
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int ret = NO_ERROR;
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struct lcdc_panel_info *lcdc = NULL;
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uint32_t mdp_rgb_size;
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int access_secure = 0;
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uint32_t mdss_mdp_intf_off = 0;
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if (pinfo == NULL)
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return ERR_INVALID_ARGS;
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lcdc = &(pinfo->lcdc);
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if (lcdc == NULL)
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return ERR_INVALID_ARGS;
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mdss_mdp_intf_off = mdss_mdp_intf_offset();
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/* write active region size*/
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mdp_rgb_size = (fb->height << 16) + fb->width;
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access_secure = restore_secure_cfg(SECURE_DEVICE_MDSS);
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mdp_clk_gating_ctrl();
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writel(0x0100, MDP_DISP_INTF_SEL);
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/* Ignore TZ return value till it's fixed */
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if (!access_secure || 1) {
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/* Force VBIF Clocks on */
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writel(0x1, VBIF_VBIF_DDR_FORCE_CLK_ON);
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/* Configure DDR burst length */
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writel(0x00000707, VBIF_VBIF_DDR_OUT_MAX_BURST);
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writel(0x00000030, VBIF_VBIF_DDR_ARB_CTRL );
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writel(0x00000001, VBIF_VBIF_DDR_RND_RBN_QOS_ARB);
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writel(0x00000FFF, VBIF_VBIF_DDR_OUT_AOOO_AXI_EN);
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writel(0x0FFF0FFF, VBIF_VBIF_DDR_OUT_AX_AOOO);
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writel(0x22222222, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0);
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writel(0x00002222, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1);
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}
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/* Allocate SMP blocks */
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writel(0x00101010, MMSS_MDP_SMP_ALLOC_W_0);
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writel(0x00000010, MMSS_MDP_SMP_ALLOC_W_1);
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writel(0x00101010, MMSS_MDP_SMP_ALLOC_R_0);
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writel(0x00000010, MMSS_MDP_SMP_ALLOC_R_1);
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writel(fb->base, MDP_VP_0_RGB_0_SSPP_SRC0_ADDR);
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writel((fb->stride * fb->bpp/8),MDP_VP_0_RGB_0_SSPP_SRC_YSTRIDE);
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writel(mdp_rgb_size, MDP_VP_0_RGB_0_SSPP_SRC_IMG_SIZE);
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writel(mdp_rgb_size, MDP_VP_0_RGB_0_SSPP_SRC_SIZE);
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writel(mdp_rgb_size, MDP_VP_0_RGB_0_SSPP_SRC_OUT_SIZE);
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writel(0x00, MDP_VP_0_RGB_0_SSPP_SRC_XY);
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writel(0x00, MDP_VP_0_RGB_0_SSPP_OUT_XY);
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/* Tight Packing 3bpp 0-Alpha 8-bit R B G */
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writel(0x0002243F, MDP_VP_0_RGB_0_SSPP_SRC_FORMAT);
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writel(0x00020001, MDP_VP_0_RGB_0_SSPP_SRC_UNPACK_PATTERN);
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writel(0x00, MDP_VP_0_RGB_0_SSPP_SRC_OP_MODE);
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writel(mdp_rgb_size,MDP_VP_0_LAYER_0_OUT_SIZE);
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writel(0x00, MDP_VP_0_LAYER_0_OP_MODE);
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writel(0x100, MDP_VP_0_LAYER_0_BLEND_OP);
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writel(0xFF, MDP_VP_0_LAYER_0_BLEND0_FG_ALPHA);
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writel(0x100, MDP_VP_0_LAYER_1_BLEND_OP);
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writel(0xFF, MDP_VP_0_LAYER_1_BLEND0_FG_ALPHA);
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writel(0x100, MDP_VP_0_LAYER_2_BLEND_OP);
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writel(0xFF, MDP_VP_0_LAYER_2_BLEND0_FG_ALPHA);
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writel(0x100, MDP_VP_0_LAYER_3_BLEND_OP);
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writel(0xFF, MDP_VP_0_LAYER_3_BLEND0_FG_ALPHA);
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/* Baselayer for layer mixer 0 */
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writel(0x00000200, MDP_CTL_0_LAYER_0);
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writel(0x213F, MDP_INTF_1_PANEL_FORMAT + mdss_mdp_intf_off);
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writel(0x20020, MDP_CTL_0_TOP);
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return ret;
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}
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int mdp_dsi_video_on(void)
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{
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int ret = NO_ERROR;
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writel(0x32048, MDP_CTL_0_FLUSH);
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writel(0x01, MDP_INTF_1_TIMING_ENGINE_EN + mdss_mdp_intf_offset());
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return ret;
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}
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int mdp_dsi_video_off()
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{
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if(!target_cont_splash_screen())
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{
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writel(0x00000000, MDP_INTF_1_TIMING_ENGINE_EN +
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mdss_mdp_intf_offset());
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mdelay(60);
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/* Ping-Pong done Tear Check Read/Write */
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/* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */
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writel(0xFF777713, MDP_INTR_CLEAR);
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}
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writel(0x00000000, MDP_INTR_EN);
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return NO_ERROR;
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}
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int mdp_dsi_cmd_off()
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{
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if(!target_cont_splash_screen())
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{
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/* Ping-Pong done Tear Check Read/Write */
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/* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */
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writel(0xFF777713, MDP_INTR_CLEAR);
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}
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writel(0x00000000, MDP_INTR_EN);
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return NO_ERROR;
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}
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int mdp_dma_on(void)
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{
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writel(0x32048, MDP_CTL_0_FLUSH);
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writel(0x01, MDP_CTL_0_START);
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return NO_ERROR;
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}
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void mdp_disable(void)
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{
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}
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