178 lines
5.7 KiB
C
178 lines
5.7 KiB
C
/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of The Linux Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#include <stdint.h>
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#include <reg.h>
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#include <err.h>
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#include <bits.h>
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#include <platform/iomap.h>
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#include <platform/clock.h>
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#include <dev/fbcon.h>
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#include <dev/lcdc.h>
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#include <msm_panel.h>
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#define MDP_OUTP(addr, val) writel(val, addr);
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void lvds_init(struct msm_panel_info *pinfo)
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{
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unsigned int lvds_intf, lvds_phy_cfg0;
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MDP_OUTP(MDP_BASE + 0xc2034, 0x33);
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udelay(1000);
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/*1. Configure LVDS PHY PLL through MDP_LVDSPHY_PLL_CTRL_* registers*/
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/* LVDS PHY PLL configuration */
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MDP_OUTP(MDP_BASE + 0xc3000, 0x08);
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MDP_OUTP(MDP_BASE + 0xc3004, 0x87);
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MDP_OUTP(MDP_BASE + 0xc3008, 0x30);
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MDP_OUTP(MDP_BASE + 0xc300c, 0x06);
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MDP_OUTP(MDP_BASE + 0xc3014, 0x20);
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MDP_OUTP(MDP_BASE + 0xc3018, 0x0F);
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MDP_OUTP(MDP_BASE + 0xc301c, 0x01);
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MDP_OUTP(MDP_BASE + 0xc3020, 0x41);
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MDP_OUTP(MDP_BASE + 0xc3024, 0x0d);
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MDP_OUTP(MDP_BASE + 0xc3028, 0x07);
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MDP_OUTP(MDP_BASE + 0xc302c, 0x00);
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MDP_OUTP(MDP_BASE + 0xc3030, 0x1c);
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MDP_OUTP(MDP_BASE + 0xc3034, 0x01);
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MDP_OUTP(MDP_BASE + 0xc3038, 0x00);
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MDP_OUTP(MDP_BASE + 0xc3040, 0xC0);
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MDP_OUTP(MDP_BASE + 0xc3044, 0x00);
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MDP_OUTP(MDP_BASE + 0xc3048, 0x30);
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MDP_OUTP(MDP_BASE + 0xc304c, 0x00);
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MDP_OUTP(MDP_BASE + 0xc3000, 0x11);
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MDP_OUTP(MDP_BASE + 0xc3064, 0x05);
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MDP_OUTP(MDP_BASE + 0xc3050, 0x20);
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/*2. Enable LVDS PHY PLL in MDP_LVDSPHY_PLL_CTRL_0*/
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MDP_OUTP(MDP_BASE + 0xc3000, 0x01);
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/*3. Poll the MDP_LVDSPHY_PLL_RDY register until it is 1*/
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/* Wait until LVDS PLL is locked and ready */
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while (!readl(MDP_BASE + 0xc3080))
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udelay(1);
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/*4. Enable dsi2_pixel domain clocks*/
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writel(0x00, REG_MM(0x0264));
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writel(0x00, REG_MM(0x0094));
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writel(0x02, REG_MM(0x00E4));
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writel((0x80 | readl(REG_MM(0x00E4))),
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REG_MM(0x00E4));
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udelay(1000);
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writel((~0x80 & readl(REG_MM(0x00E4))),
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REG_MM(0x00E4));
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writel(0x05, REG_MM(0x0094));
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writel(0x02, REG_MM(0x0264));
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/* Wait until LVDS pixel clock output is enabled */
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dsb();
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if (pinfo->bpp == 24) {
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/* MDP_LCDC_LVDS_MUX_CTL_FOR_D0_3_TO_0 */
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MDP_OUTP(MDP_BASE + 0xc2014, 0x03040508);
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/* MDP_LCDC_LVDS_MUX_CTL_FOR_D0_6_TO_4 */
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MDP_OUTP(MDP_BASE + 0xc2018, 0x00000102);
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/* MDP_LCDC_LVDS_MUX_CTL_FOR_D1_3_TO_0 */
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MDP_OUTP(MDP_BASE + 0xc201c, 0x0c0d1011);
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/* MDP_LCDC_LVDS_MUX_CTL_FOR_D1_6_TO_4 */
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MDP_OUTP(MDP_BASE + 0xc2020, 0x00090a0b);
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/* MDP_LCDC_LVDS_MUX_CTL_FOR_D2_3_TO_0 */
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MDP_OUTP(MDP_BASE + 0xc2024, 0x151a191a);
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/* MDP_LCDC_LVDS_MUX_CTL_FOR_D2_6_TO_4 */
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MDP_OUTP(MDP_BASE + 0xc2028, 0x00121314);
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/* MDP_LCDC_LVDS_MUX_CTL_FOR_D3_3_TO_0 */
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MDP_OUTP(MDP_BASE + 0xc202c, 0x1706071b);
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/* MDP_LCDC_LVDS_MUX_CTL_FOR_D3_6_TO_4 */
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MDP_OUTP(MDP_BASE + 0xc2030, 0x000e0f16);
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if (pinfo->lvds.channel_mode ==
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LVDS_DUAL_CHANNEL_MODE) {
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lvds_intf = 0x0001ff80;
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lvds_phy_cfg0 = BIT(6) | BIT(7);
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if (pinfo->lvds.channel_swap)
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lvds_intf |= BIT(4);
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} else {
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lvds_intf = 0x00010f84;
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lvds_phy_cfg0 = BIT(6);
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}
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} else if (pinfo->bpp == 18) {
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/* MDP_LCDC_LVDS_MUX_CTL_FOR_D0_3_TO_0 */
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MDP_OUTP(MDP_BASE + 0xc2014, 0x03040508);
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/* MDP_LCDC_LVDS_MUX_CTL_FOR_D0_6_TO_4 */
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MDP_OUTP(MDP_BASE + 0xc2018, 0x00000102);
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/* MDP_LCDC_LVDS_MUX_CTL_FOR_D1_3_TO_0 */
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MDP_OUTP(MDP_BASE + 0xc201c, 0x0c0d1011);
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/* MDP_LCDC_LVDS_MUX_CTL_FOR_D1_6_TO_4 */
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MDP_OUTP(MDP_BASE + 0xc2020, 0x00090a0b);
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/* MDP_LCDC_LVDS_MUX_CTL_FOR_D2_3_TO_0 */
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MDP_OUTP(MDP_BASE + 0xc2024, 0x1518191a);
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/* MDP_LCDC_LVDS_MUX_CTL_FOR_D2_6_TO_4 */
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MDP_OUTP(MDP_BASE + 0xc2028, 0x00121314);
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if (pinfo->lvds.channel_mode ==
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LVDS_DUAL_CHANNEL_MODE) {
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lvds_intf = 0x00017788;
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lvds_phy_cfg0 = BIT(6) | BIT(7);
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if (pinfo->lvds.channel_swap)
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lvds_intf |= BIT(4);
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} else {
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lvds_intf = 0x0001078c;
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lvds_phy_cfg0 = BIT(6);
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}
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}
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/* MDP_LVDSPHY_CFG0 */
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MDP_OUTP(MDP_BASE + 0xc3100, lvds_phy_cfg0);
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/* MDP_LCDC_LVDS_INTF_CTL */
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MDP_OUTP(MDP_BASE + 0xc2000, lvds_intf);
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MDP_OUTP(MDP_BASE + 0xc3108, 0x30);
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lvds_phy_cfg0 |= BIT(4);
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/* Wait until LVDS PHY registers are configured */
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dsb();
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udelay(1);
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/* MDP_LVDSPHY_CFG0, enable serialization */
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MDP_OUTP(MDP_BASE + 0xc3100, lvds_phy_cfg0);
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}
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int lvds_on(struct msm_fb_panel_data *pdata)
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{
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int ret = 0;
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if (pdata == NULL) {
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ret = ERR_INVALID_ARGS;
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goto out;
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}
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lvds_init(&(pdata->panel_info));
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out:
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return ret;
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}
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