342 lines
13 KiB
C
342 lines
13 KiB
C
/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of The Linux Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __PLATFORM_SDHCI_H_
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#define __PLATFORM_SDHCI_H_
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#include <reg.h>
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#include <bits.h>
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/*
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* Capabilities for the host controller
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* These values are read from the capabilities
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* register in the controller
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*/
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struct host_caps {
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uint32_t base_clk_rate; /* Max clock rate supported */
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uint32_t max_blk_len; /* Max block len supported */
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uint8_t bus_width_8bit; /* 8 Bit mode supported */
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uint8_t adma_support; /* Adma support */
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uint8_t voltage; /* Supported voltage */
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uint8_t sdr_support; /* Single Data rate */
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uint8_t ddr_support; /* Dual Data rate */
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uint8_t sdr50_support; /* UHS mode, with 100 MHZ clock */
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};
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/*
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* sdhci host structure, holding information about host
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* controller parameters
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*/
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struct sdhci_host {
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uint32_t base; /* Base address for the host */
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uint32_t cur_clk_rate; /* Running clock rate */
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struct host_caps caps; /* Host capabilities */
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};
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/*
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* Data pointer to be read/written
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*/
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struct mmc_data {
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void *data_ptr; /* Points to stream of data */
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uint32_t blk_sz; /* Block size for the data */
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uint32_t num_blocks; /* num of blocks, each always of size SDHCI_MMC_BLK_SZ */
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};
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/*
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* mmc command structure as per the spec
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*/
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struct mmc_command {
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uint16_t cmd_index; /* Command index */
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uint32_t argument; /* Command argument */
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uint8_t data_present; /* Command has data */
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uint8_t cmd_type; /* command type */
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uint16_t resp_type; /* Response type of the command */
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uint32_t resp[4]; /* 128 bit response value */
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uint32_t trans_mode; /* Transfer mode, read/write */
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uint32_t cmd_retry; /* Retry the command, if card is busy */
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struct mmc_data data; /* Data pointer */
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};
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/*
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* Descriptor table for adma
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*/
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struct desc_entry {
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uint16_t tran_att; /* Attribute for transfer data */
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uint16_t len; /* Length of data */
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void *addr; /* Address of the data */
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};
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/*
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* Command types for sdhci
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*/
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enum {
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SDHCI_CMD_TYPE_NORMAL = 0,
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SDHCI_CMD_TYPE_SUSPEND,
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SDHCI_CMD_TYPE_RESUME,
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SDHCI_CMD_TYPE_ABORT,
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} sdhci_cmd_type;
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/*
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* Response type values for sdhci
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*/
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enum {
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SDHCI_CMD_RESP_NONE = 0,
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SDHCI_CMD_RESP_136,
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SDHCI_CMD_RESP_48,
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SDHCI_CMD_RESP_48_BUSY,
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} sdhci_resp_type;
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/*
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* Helper macros for writing byte, word & long registers
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*/
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#define REG_READ8(host, a) readb(host->base + a);
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#define REG_WRITE8(host, v, a) writeb(v, (host->base + a))
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#define REG_READ32(host, a) readl(host->base + a)
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#define REG_WRITE32(host, v, a) writel(v, (host->base + a))
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#define REG_READ16(host, a) readhw(host->base + a)
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#define REG_WRITE16(host, v, a) writehw(v, (host->base + a))
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/*
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* SDHCI registers, as per the host controller spec v 3.0
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*/
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#define SDHCI_ARG2_REG (0x000)
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#define SDHCI_BLKSZ_REG (0x004)
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#define SDHCI_BLK_CNT_REG (0x006)
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#define SDHCI_ARGUMENT_REG (0x008)
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#define SDHCI_TRANS_MODE_REG (0x00C)
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#define SDHCI_CMD_REG (0x00E)
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#define SDHCI_RESP_REG (0x010)
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#define SDHCI_PRESENT_STATE_REG (0x024)
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#define SDHCI_HOST_CTRL1_REG (0x028)
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#define SDHCI_PWR_CTRL_REG (0x029)
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#define SDHCI_CLK_CTRL_REG (0x02C)
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#define SDHCI_TIMEOUT_REG (0x02E)
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#define SDHCI_RESET_REG (0x02F)
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#define SDHCI_NRML_INT_STS_REG (0x030)
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#define SDHCI_ERR_INT_STS_REG (0x032)
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#define SDHCI_NRML_INT_STS_EN_REG (0x034)
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#define SDHCI_ERR_INT_STS_EN_REG (0x036)
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#define SDHCI_NRML_INT_SIG_EN_REG (0x038)
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#define SDHCI_ERR_INT_SIG_EN_REG (0x03A)
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#define SDHCI_HOST_CTRL2_REG (0x03E)
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#define SDHCI_CAPS_REG1 (0x040)
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#define SDHCI_CAPS_REG2 (0x044)
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#define SDHCI_ADM_ADDR_REG (0x058)
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/*
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* Helper macros for register writes
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*/
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#define SDHCI_SOFT_RESET BIT(0)
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#define SOFT_RESET_CMD BIT(1)
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#define SOFT_RESET_DATA BIT(2)
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#define SDHCI_1_8_VOL_SET BIT(3)
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/*
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* Interrupt related
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*/
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#define SDHCI_NRML_INT_STS_EN 0x000B
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#define SDHCI_ERR_INT_STS_EN 0xFFFF
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#define SDHCI_NRML_INT_SIG_EN 0x000B
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#define SDHCI_ERR_INT_SIG_EN 0xFFFF
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#define SDCC_HC_INT_CARD_REMOVE BIT(7)
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#define SDCC_HC_INT_CARD_INSERT BIT(6)
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/*
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* HC mode enable/disable
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*/
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#define SDHCI_HC_MODE_EN BIT(0)
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#define SDHCI_HC_MODE_DIS (0 << 1)
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/*
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* Clk control related
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*/
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#define SDHCI_CLK_MAX_DIV 2046
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#define SDHCI_SDCLK_FREQ_SEL 8
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#define SDHCI_SDCLK_UP_BIT_SEL 6
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#define SDHCI_SDCLK_FREQ_MASK 0xFF
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#define SDHC_SDCLK_UP_BIT_MASK 0x300
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#define SDHCI_INT_CLK_EN BIT(0)
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#define SDHCI_CLK_STABLE_MASK BIT(1)
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#define SDHCI_CLK_STABLE BIT(1)
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#define SDHCI_CLK_EN BIT(2)
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#define SDHCI_CLK_DIS (0 << 2)
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#define SDHCI_CLK_RATE_MASK 0x0000FF00
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#define SDHCI_CLK_RATE_BIT 8
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#define SDHCI_CMD_ACT BIT(0)
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#define SDHCI_DAT_ACT BIT(1)
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/*
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* Bus voltage related macros
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*/
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#define SDHCI_BUS_VOL_SEL 1
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#define SDHCI_BUS_PWR_EN BIT(0)
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#define SDHCI_VOL_1_8 5
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#define SDHCI_VOL_3_0 6
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#define SDHCI_VOL_3_3 7
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#define SDHCI_3_3_VOL_MASK 0x01000000
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#define SDHCI_3_0_VOL_MASK 0x02000000
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#define SDHCI_1_8_VOL_MASK 0x04000000
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/*
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* Bus width related macros
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*/
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#define SDHCI_8BIT_WIDTH_MASK 0x00040000
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#define SDHCI_BUS_WITDH_1BIT (0)
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#define SDHCI_BUS_WITDH_4BIT BIT(1)
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#define SDHCI_BUS_WITDH_8BIT BIT(5)
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/*
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* Adma related macros
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*/
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#define SDHCI_BLK_LEN_MASK 0x00030000
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#define SDHCI_BLK_LEN_BIT 16
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#define SDHCI_BLK_ADMA_MASK 0x00080000
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#define SDHCI_INT_STS_TRANS_COMPLETE BIT(1)
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#define SDHCI_STATE_CMD_DAT_MASK 0x0003
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#define SDHCI_INT_STS_CMD_COMPLETE BIT(0)
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#define SDHCI_ERR_INT_STAT_MASK 0x8000
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#define SDHCI_ADMA_DESC_LINE_SZ 65536
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#define SDHCI_ADMA_MAX_TRANS_SZ (65535 * 512)
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#define SDHCI_ADMA_TRANS_VALID BIT(0)
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#define SDHCI_ADMA_TRANS_END BIT(1)
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#define SDHCI_ADMA_TRANS_DATA BIT(5)
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#define SDHCI_MMC_BLK_SZ 512
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#define SDHCI_MMC_CUR_BLK_CNT_BIT 16
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#define SDHCI_MMC_BLK_SZ_BIT 0
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#define SDHCI_TRANS_MULTI BIT(5)
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#define SDHCI_TRANS_SINGLE (0 << 5)
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#define SDHCI_BLK_CNT_EN BIT(1)
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#define SDHCI_DMA_EN BIT(0)
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#define SDHCI_AUTO_CMD23_EN BIT(3)
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#define SDHCI_ADMA_32BIT BIT(4)
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/*
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* Command related macros
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*/
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#define SDHCI_CMD_RESP_TYPE_SEL_BIT 0
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#define SDHCI_CMD_CRC_CHECK_BIT 3
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#define SDHCI_CMD_IDX_CHECK_BIT 4
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#define SDHCI_CMD_DATA_PRESENT_BIT 5
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#define SDHCI_CMD_CMD_TYPE_BIT 6
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#define SDHCI_CMD_CMD_IDX_BIT 8
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#define SDHCI_CMD_TIMEOUT_MASK BIT(0)
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#define SDHCI_CMD_CRC_MASK BIT(1)
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#define SDHCI_CMD_END_BIT_MASK BIT(2)
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#define SDHCI_CMD_IDX_MASK BIT(3)
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#define SDHCI_DAT_TIMEOUT_MASK BIT(4)
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#define SDHCI_DAT_CRC_MASK BIT(5)
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#define SDHCI_DAT_END_BIT_MASK BIT(6)
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#define SDHCI_CUR_LIM_MASK BIT(7)
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#define SDHCI_AUTO_CMD12_MASK BIT(8)
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#define SDHCI_ADMA_MASK BIT(9)
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#define SDHCI_READ_MODE BIT(4)
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#define SDHCI_SWITCH_CMD 6
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#define SDHCI_CMD_TIMEOUT 0xE
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#define SDHCI_MAX_CMD_RETRY 10000
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#define SDHCI_MAX_TRANS_RETRY 100000
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#define SDHCI_PREP_CMD(c, f) ((((c) & 0xff) << 8) | ((f) & 0xff))
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/*
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* command response related
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*/
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#define SDHCI_RESP_LSHIFT 8
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#define SDHCI_RESP_RSHIFT 24
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/*
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* Power control relatd macros
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*/
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#define SDHCI_SOFT_RESET_MASK (BIT(0) | BIT(1) | BIT(2))
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#define SDCC_HC_PWR_CTRL_INT 0xF
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#define SDCC_HC_BUS_ON BIT(0)
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#define SDCC_HC_BUS_OFF BIT(1)
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#define SDCC_HC_BUS_ON_OFF_SUCC BIT(0)
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#define SDCC_HC_IO_SIG_LOW BIT(2)
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#define SDCC_HC_IO_SIG_HIGH BIT(3)
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#define SDCC_HC_IO_SIG_SUCC BIT(2)
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/*
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* Command response
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*/
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#define SDHCI_CMD_RESP_NONE 0
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#define SDHCI_CMD_RESP_R1 BIT(0)
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#define SDHCI_CMD_RESP_R1B BIT(1)
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#define SDHCI_CMD_RESP_R2 BIT(2)
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#define SDHCI_CMD_RESP_R3 BIT(3)
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#define SDHCI_CMD_RESP_R6 BIT(6)
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#define SDHCI_CMD_RESP_R7 BIT(7)
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/*
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* Clock Divider values
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*/
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#define SDHCI_CLK_400KHZ 400000
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#define SDHCI_CLK_25MHZ 25000000
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#define SDHCI_CLK_50MHZ 50000000
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#define SDHCI_CLK_100MHZ 100000000
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#define SDHCI_CLK_200MHZ 200000000
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/* DDR mode related macros */
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#define SDHCI_DDR_MODE_EN 0x0004
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#define SDHCI_DDR_MODE_MASK BIT(2)
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/* HS200/SDR50 mode related macros */
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#define SDHCI_SDR50_MODE_MASK BIT(0)
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#define SDHCI_SDR50_MODE_EN 0x0002
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/*
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* APIs and macros exposed for mmc/sd drivers
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*/
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#define SDHCI_MMC_WRITE 0
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#define SDHCI_MMC_READ 1
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#define DATA_BUS_WIDTH_1BIT 0
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#define DATA_BUS_WIDTH_4BIT 1
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#define DATA_BUS_WIDTH_8BIT 2
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#define DATA_DDR_BUS_WIDTH_4BIT 5
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#define DATA_DDR_BUS_WIDTH_8BIT 6
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/* API: to initialize the controller */
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void sdhci_init(struct sdhci_host *);
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/* API: Send the command & transfer data using adma */
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uint32_t sdhci_send_command(struct sdhci_host *, struct mmc_command *);
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/* API: Set the bus width for the contoller */
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uint8_t sdhci_set_bus_width(struct sdhci_host *, uint16_t);
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/* API: Clock supply for the controller */
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uint32_t sdhci_clk_supply(struct sdhci_host *, uint32_t);
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/* API: Enable DDR mode */
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void sdhci_set_ddr_mode(struct sdhci_host *);
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/* API: To enable SDR mode */
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void sdhci_set_sdr_mode(struct sdhci_host *);
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#endif
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