531 lines
16 KiB
C
531 lines
16 KiB
C
/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of The Linux Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <reg.h>
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#include <debug.h>
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#include <endian.h>
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#include <stdlib.h>
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#include <arch/ops.h>
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#include <platform.h>
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#include <platform/iomap.h>
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#include <clock.h>
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#include <platform/clock.h>
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#include <crypto5_eng.h>
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#define CLEAR_STATUS(dev) crypto_write_reg(&dev->bam, CRYPTO_STATUS(dev->base), 0, BAM_DESC_UNLOCK_FLAG)
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#define CONFIG_WRITE(dev, val) crypto_write_reg(&dev->bam, CRYPTO_CONFIG(dev->base), val, BAM_DESC_LOCK_FLAG)
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#define REG_WRITE(dev, addr, val) crypto_write_reg(&dev->bam, addr, val, 0)
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#ifndef CRYPTO_REG_ACCESS
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#define CE_INIT(dev) dev->ce_array_index = 0; dev->cd_start = 0
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#define ADD_WRITE_CE(dev, addr, val) crypto_add_cmd_element(dev, addr, val)
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#define ADD_CMD_DESC(dev, flags) crypto_add_cmd_desc(dev, flags)
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#define CMD_EXEC(bam, num_desc, pipe) crypto_wait_for_cmd_exec(bam, num_desc, pipe)
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#define REG_WRITE_QUEUE_INIT(dev) CE_INIT(dev)
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#define REG_WRITE_QUEUE(dev, addr, val) ADD_WRITE_CE(dev, addr, val)
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#define REG_WRITE_QUEUE_DONE(dev, flags) ADD_CMD_DESC(dev, flags)
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#define REG_WRITE_EXEC(bam, num_desc, pipe) CMD_EXEC(bam, num_desc, pipe)
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#else
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#define REG_WRITE_QUEUE_INIT(dev) /* nop */
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#define REG_WRITE_QUEUE(dev, addr, val) writel(val, addr)
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#define REG_WRITE_QUEUE_DONE(dev, flags) /* nop */
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#define REG_WRITE_EXEC(bam, num_desc, pipe) /* nop */
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#endif
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#define ADD_READ_DESC(bam, buf_addr, buf_size, flags) bam_add_desc(bam, CRYPTO_READ_PIPE_INDEX, buf_addr, buf_size, flags)
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#define ADD_WRITE_DESC(bam, buf_addr, buf_size, flags) bam_add_desc(bam, CRYPTO_WRITE_PIPE_INDEX, buf_addr, buf_size, flags)
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static struct bam_desc *crypto_allocate_fifo(uint32_t size)
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{
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struct bam_desc *ptr;
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ptr = (struct bam_desc *) memalign(lcm(CACHE_LINE, BAM_DESC_SIZE),
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ROUNDUP(size * BAM_DESC_SIZE, CACHE_LINE));
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if (ptr == NULL)
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dprintf(CRITICAL, "Could not allocate fifo buffer\n");
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return ptr;
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}
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static struct output_dump *crypto_allocate_dump_buffer(void)
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{
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struct output_dump *ptr;
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ptr = (struct output_dump *) memalign(lcm(CACHE_LINE, CRYPTO_BURST_LEN),
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ROUNDUP(sizeof(struct output_dump), CACHE_LINE));
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if (ptr == NULL)
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dprintf(CRITICAL, "Could not allocate output dump buffer\n");
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return ptr;
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}
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static struct cmd_element *crypto_allocate_ce_array(uint32_t size)
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{
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struct cmd_element *ptr = NULL;
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#ifndef CRYPTO_REG_ACCESS
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ptr = (struct cmd_element*) memalign(CACHE_LINE,
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ROUNDUP(size * sizeof(struct cmd_element), CACHE_LINE));
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if (ptr == NULL)
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dprintf(CRITICAL, "Could not allocate ce array buffer\n");
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#endif
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return ptr;
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}
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static void crypto_wait_for_cmd_exec(struct bam_instance *bam_core,
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uint32_t num_desc,
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uint8_t pipe)
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{
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/* Create a read/write event to notify the periperal of the added desc. */
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bam_sys_gen_event(bam_core, pipe, num_desc);
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/* Wait for the descriptors to be processed */
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bam_wait_for_interrupt(bam_core, pipe, P_PRCSD_DESC_EN_MASK);
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/* Read offset update for the circular FIFO */
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bam_read_offset_update(bam_core, pipe);
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}
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static void crypto_wait_for_data(struct bam_instance *bam, uint32_t pipe_num)
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{
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/* Wait for the descriptors to be processed */
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bam_wait_for_interrupt(bam, pipe_num, P_PRCSD_DESC_EN_MASK);
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/* Read offset update for the circular FIFO */
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bam_read_offset_update(bam, pipe_num);
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}
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static uint32_t crypto_write_reg(struct bam_instance *bam_core,
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uint32_t reg_addr,
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uint32_t val,
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uint8_t flags)
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{
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uint32_t ret = 0;
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struct cmd_element cmd_list_ptr;
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#ifdef CRYPTO_REG_ACCESS
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writel(val, reg_addr);
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#else
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ret = (uint32_t)bam_add_cmd_element(&cmd_list_ptr, reg_addr, val, CE_WRITE_TYPE);
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/* Enqueue the desc for the above command */
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ret = bam_add_one_desc(bam_core,
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CRYPTO_WRITE_PIPE_INDEX,
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(unsigned char*)PA((addr_t)&cmd_list_ptr),
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BAM_CE_SIZE,
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BAM_DESC_CMD_FLAG | BAM_DESC_INT_FLAG | flags);
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if (ret)
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{
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dprintf(CRITICAL,
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"CRYPTO_WRITE_REG: Reg write failed. reg addr = %x\n",
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reg_addr);
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goto crypto_read_reg_err;
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}
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crypto_wait_for_cmd_exec(bam_core, 1, CRYPTO_WRITE_PIPE_INDEX);
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#endif
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crypto_read_reg_err:
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return ret;
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}
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static void crypto_add_cmd_element(struct crypto_dev *dev,
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uint32_t addr,
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uint32_t val)
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{
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struct cmd_element *ptr = dev->ce_array;
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bam_add_cmd_element(&(ptr[dev->ce_array_index]), addr, val, CE_WRITE_TYPE);
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arch_clean_invalidate_cache_range((addr_t) &(ptr[dev->ce_array_index]), sizeof(struct cmd_element));
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dev->ce_array_index++;
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}
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static void crypto_add_cmd_desc(struct crypto_dev *dev, uint8_t flags)
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{
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uint32_t ce_size;
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uint32_t start = (uint32_t)&(dev->ce_array[dev->cd_start]);
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uint32_t ret;
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ce_size = (uint32_t)&(dev->ce_array[dev->ce_array_index]) - start;
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ret = bam_add_one_desc(&dev->bam,
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CRYPTO_WRITE_PIPE_INDEX,
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(unsigned char*)start,
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ce_size,
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BAM_DESC_CMD_FLAG | flags);
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if (ret)
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{
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dprintf(CRITICAL, "CRYPTO_ADD_DESC: Adding desc failed\n");
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}
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/* Update the CD ptr. */
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dev->cd_start = dev->ce_array_index;
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}
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static int crypto_bam_init(struct crypto_dev *dev)
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{
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uint32_t bam_ret;
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/* Do BAM Init only if required. */
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if (dev->do_bam_init)
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bam_init(&dev->bam);
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/* Initialize BAM CRYPTO read pipe */
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bam_sys_pipe_init(&dev->bam, CRYPTO_READ_PIPE_INDEX);
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/* Init read fifo */
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bam_ret = bam_pipe_fifo_init(&dev->bam, CRYPTO_READ_PIPE_INDEX);
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if (bam_ret)
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{
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dprintf(CRITICAL, "CRYPTO: BAM Read FIFO init error\n");
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bam_ret = CRYPTO_ERR_FAIL;
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goto crypto_bam_init_err;
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}
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/* Initialize BAM CRYPTO write pipe */
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bam_sys_pipe_init(&dev->bam, CRYPTO_WRITE_PIPE_INDEX);
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/* Init write fifo. Use the same fifo as read fifo. */
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bam_ret = bam_pipe_fifo_init(&dev->bam, CRYPTO_WRITE_PIPE_INDEX);
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if (bam_ret)
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{
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dprintf(CRITICAL, "CRYPTO: BAM Write FIFO init error\n");
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bam_ret = CRYPTO_ERR_FAIL;
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goto crypto_bam_init_err;
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}
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bam_ret = CRYPTO_ERR_NONE;
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crypto_bam_init_err:
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return bam_ret;
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}
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static void crypto_reset(struct crypto_dev *dev)
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{
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clock_config_ce(dev->instance);
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}
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void crypto5_init_params(struct crypto_dev *dev, struct crypto_init_params *params)
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{
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dev->base = params->crypto_base;
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dev->instance = params->crypto_instance;
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dev->bam.base = params->bam_base;
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dev->do_bam_init = params->do_bam_init;
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/* Set Read pipe params. */
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dev->bam.pipe[CRYPTO_READ_PIPE_INDEX].pipe_num = params->pipes.read_pipe;
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/* System consumer */
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dev->bam.pipe[CRYPTO_READ_PIPE_INDEX].trans_type = BAM2SYS;
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dev->bam.pipe[CRYPTO_READ_PIPE_INDEX].fifo.size = params->read_fifo_size;
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dev->bam.pipe[CRYPTO_READ_PIPE_INDEX].fifo.head = crypto_allocate_fifo(params->read_fifo_size);
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/* Set Write pipe params. */
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dev->bam.pipe[CRYPTO_WRITE_PIPE_INDEX].pipe_num = params->pipes.write_pipe;
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/* System producer */
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dev->bam.pipe[CRYPTO_WRITE_PIPE_INDEX].trans_type = SYS2BAM;
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dev->bam.pipe[CRYPTO_WRITE_PIPE_INDEX].fifo.size = params->write_fifo_size;
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dev->bam.pipe[CRYPTO_WRITE_PIPE_INDEX].fifo.head = crypto_allocate_fifo(params->write_fifo_size);
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dev->bam.threshold = CRYPTO_MAX_THRESHOLD;
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dev->bam.ee = params->bam_ee;
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/* A H/W bug on Crypto 5.0.0 enforces a rule that the desc lengths must be burst aligned. */
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dev->bam.max_desc_len = ROUNDDOWN(BAM_NDP_MAX_DESC_DATA_LEN, CRYPTO_BURST_LEN);
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dev->dump = crypto_allocate_dump_buffer();
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dev->ce_array = crypto_allocate_ce_array(params->num_ce);
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dev->ce_array_index = 0;
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dev->cd_start = 0;
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}
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void crypto5_init(struct crypto_dev *dev)
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{
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uint32_t config = CRYPTO_RESET_CONFIG
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| (dev->bam.pipe[CRYPTO_READ_PIPE_INDEX].pipe_num >> 1) << PIPE_SET_SELECT_SHIFT;
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/* Configure CE clocks. */
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clock_config_ce(dev->instance);
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/* Setup BAM */
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if (crypto_bam_init(dev) != CRYPTO_ERR_NONE)
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{
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dprintf(CRITICAL, "CRYPTO: BAM init error\n");
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goto crypto_init_err;
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}
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/* Write basic config to CE.
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* Note: This setting will be changed to be set from TZ.
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*/
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writel(config, CRYPTO_CONFIG(dev->base));
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config = 0;
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/* Setup config reg. */
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/* Mask all irqs. */
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config |= MASK_ERR_INTR | MASK_OP_DONE_INTR |
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MASK_DIN_INTR | MASK_DOUT_INTR;
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/* Program BAM specific crypto settings. */
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config |= HIGH_SPD_IN_EN_N
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| ((dev->bam.pipe[CRYPTO_WRITE_PIPE_INDEX].pipe_num >> 1) << PIPE_SET_SELECT_SHIFT)
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| MAX_QUEUED_REQS
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| REQ_SIZE;
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/* Use a few registers in little endian mode. */
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config |= LITTLE_ENDIAN_MODE;
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CONFIG_WRITE(dev, config);
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crypto_init_err:
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return;
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}
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static uint32_t crypto5_get_sha_cfg(void *ctx_ptr, crypto_auth_alg_type auth_alg)
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{
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crypto_SHA256_ctx *sha256_ctx = (crypto_SHA256_ctx *) ctx_ptr;
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uint32_t seg_cfg_val;
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seg_cfg_val = SEG_CFG_AUTH_ALG_SHA;
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if (auth_alg == CRYPTO_AUTH_ALG_SHA256)
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{
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seg_cfg_val |= SEG_CFG_AUTH_SIZE_SHA256;
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if (sha256_ctx->flags & CRYPTO_LAST_CHUNK)
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{
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seg_cfg_val |= SEG_CFG_LAST;
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}
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}
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else
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{
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dprintf(CRITICAL, "crypto_set_sha_ctx invalid auth algorithm\n");
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return 0;
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}
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return seg_cfg_val;
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}
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void crypto5_set_ctx(struct crypto_dev *dev,
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void *ctx_ptr,
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crypto_auth_alg_type auth_alg)
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{
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crypto_SHA256_ctx *sha256_ctx = (crypto_SHA256_ctx *) ctx_ptr;
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uint32_t i = 0;
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uint32_t iv_len = SHA256_INIT_VECTOR_SIZE;
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uint32_t *auth_iv = sha256_ctx->auth_iv;
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uint32_t seg_cfg_val;
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uint32_t total_bytes_to_write = sha256_ctx->bytes_to_write;
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uint32_t bytes_to_write = total_bytes_to_write;
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uint32_t burst_mask;
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seg_cfg_val = crypto5_get_sha_cfg(ctx_ptr, auth_alg);
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if (!seg_cfg_val)
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{
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dprintf(CRITICAL, "Authentication alg config failed.\n");
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return;
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}
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/* Initialize CE pointers. */
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REG_WRITE_QUEUE_INIT(dev);
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REG_WRITE_QUEUE(dev, CRYPTO_AUTH_SEG_CFG(dev->base), seg_cfg_val);
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for (i = 0; i < iv_len; i++)
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{
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if (sha256_ctx->flags & CRYPTO_FIRST_CHUNK)
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REG_WRITE_QUEUE(dev, CRYPTO_AUTH_IVn(dev->base, i), BE32(*(auth_iv + i)));
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else
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REG_WRITE_QUEUE(dev, CRYPTO_AUTH_IVn(dev->base, i), (*(auth_iv + i)));
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}
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/* Check if the transfer length is a 8 beat burst multiple. */
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burst_mask = CRYPTO_BURST_LEN - 1;
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if (bytes_to_write & burst_mask)
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{
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/* Add trailer to make it a burst multiple. */
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total_bytes_to_write = (bytes_to_write + burst_mask) & (~burst_mask);
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}
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sha256_ctx->bytes_to_write = total_bytes_to_write;
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/* Typecast with crypto_SHA1_ctx because offset of auth_bytecnt
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* in both crypto_SHA1_ctx and crypto_SHA256_ctx are same.
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*/
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REG_WRITE_QUEUE(dev, CRYPTO_AUTH_BYTECNTn(dev->base, 0), ((crypto_SHA1_ctx *) ctx_ptr)->auth_bytecnt[0]);
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REG_WRITE_QUEUE(dev, CRYPTO_AUTH_BYTECNTn(dev->base, 1), ((crypto_SHA1_ctx *) ctx_ptr)->auth_bytecnt[1]);
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/* Assume no header, always. */
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REG_WRITE_QUEUE(dev, CRYPTO_AUTH_SEG_START(dev->base), 0);
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REG_WRITE_QUEUE(dev, CRYPTO_AUTH_SEG_SIZE(dev->base), bytes_to_write);
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REG_WRITE_QUEUE(dev, CRYPTO_SEG_SIZE(dev->base), total_bytes_to_write);
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REG_WRITE_QUEUE(dev, CRYPTO_GOPROC(dev->base), GOPROC_GO);
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REG_WRITE_QUEUE_DONE(dev, BAM_DESC_LOCK_FLAG | BAM_DESC_INT_FLAG);
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REG_WRITE_EXEC(&dev->bam, 1, CRYPTO_WRITE_PIPE_INDEX);
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}
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uint32_t crypto5_send_data(struct crypto_dev *dev,
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void *ctx_ptr,
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uint8_t *data_ptr)
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{
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uint32_t bam_status;
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crypto_SHA256_ctx *sha256_ctx = (crypto_SHA256_ctx *) ctx_ptr;
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uint32_t wr_flags = BAM_DESC_NWD_FLAG | BAM_DESC_INT_FLAG | BAM_DESC_EOT_FLAG;
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uint32_t ret_status;
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/* A H/W bug on Crypto 5.0.0 enforces a rule that the desc lengths must be burst aligned. */
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if ((uint32_t) data_ptr & (CRYPTO_BURST_LEN - 1))
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{
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dprintf(CRITICAL, "Crypto send data failed\n");
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dprintf(CRITICAL, "Data start not aligned at burst length.\n");
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ret_status = CRYPTO_ERR_FAIL;
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goto CRYPTO_SEND_DATA_ERR;
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}
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arch_clean_invalidate_cache_range((addr_t) data_ptr, sha256_ctx->bytes_to_write);
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bam_status = ADD_WRITE_DESC(&dev->bam, data_ptr, sha256_ctx->bytes_to_write, wr_flags);
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if (bam_status)
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{
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dprintf(CRITICAL, "Crypto send data failed\n");
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ret_status = CRYPTO_ERR_FAIL;
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goto CRYPTO_SEND_DATA_ERR;
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}
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|
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arch_clean_invalidate_cache_range((addr_t) (dev->dump), sizeof(struct output_dump));
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bam_status = ADD_READ_DESC(&dev->bam,
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(unsigned char *)PA((addr_t)(dev->dump)),
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sizeof(struct output_dump),
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BAM_DESC_INT_FLAG);
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if (bam_status)
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{
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dprintf(CRITICAL, "Crypto send data failed\n");
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ret_status = CRYPTO_ERR_FAIL;
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goto CRYPTO_SEND_DATA_ERR;
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}
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crypto_wait_for_data(&dev->bam, CRYPTO_WRITE_PIPE_INDEX);
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crypto_wait_for_data(&dev->bam, CRYPTO_READ_PIPE_INDEX);
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|
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arch_clean_invalidate_cache_range((addr_t) (dev->dump), sizeof(struct output_dump));
|
|
|
|
ret_status = CRYPTO_ERR_NONE;
|
|
|
|
CRYPTO_SEND_DATA_ERR:
|
|
|
|
return ret_status;
|
|
}
|
|
|
|
void crypto5_cleanup(struct crypto_dev *dev)
|
|
{
|
|
CLEAR_STATUS(dev);
|
|
|
|
/* Free all related memory. */
|
|
free(dev->dump);
|
|
free(dev->ce_array);
|
|
free(dev->bam.pipe[CRYPTO_READ_PIPE_INDEX].fifo.head);
|
|
free(dev->bam.pipe[CRYPTO_WRITE_PIPE_INDEX].fifo.head);
|
|
}
|
|
|
|
uint32_t crypto5_get_digest(struct crypto_dev *dev,
|
|
uint8_t *digest_ptr,
|
|
crypto_auth_alg_type auth_alg)
|
|
{
|
|
uint32_t ce_status = 0;
|
|
uint32_t ce_status2 = 0;
|
|
uint32_t ce_err_bmsk = 0;
|
|
uint32_t i = 0;
|
|
uint32_t digest_len = 0;
|
|
uint32_t auth_iv;
|
|
|
|
/* Check status register for errors. */
|
|
ce_err_bmsk = (AXI_ERR | SW_ERR | HSD_ERR);
|
|
ce_status = BE32(dev->dump->status);
|
|
|
|
/* Check status register for errors. */
|
|
ce_status2 = BE32(dev->dump->status2);
|
|
|
|
if ((ce_status & ce_err_bmsk) || (ce_status2 & AXI_EXTRA))
|
|
{
|
|
crypto_reset(dev);
|
|
dprintf(CRITICAL, "crypto_get_digest status error");
|
|
dprintf(CRITICAL, "status = %x status2 = %x\n", ce_status, ce_status2);
|
|
return CRYPTO_ERR_FAIL;
|
|
}
|
|
|
|
/* Digest length depends on auth_alg */
|
|
if (auth_alg == CRYPTO_AUTH_ALG_SHA1)
|
|
{
|
|
digest_len = SHA1_INIT_VECTOR_SIZE;
|
|
}
|
|
else if (auth_alg == CRYPTO_AUTH_ALG_SHA256)
|
|
{
|
|
digest_len = SHA256_INIT_VECTOR_SIZE;
|
|
}
|
|
|
|
/* Retrieve digest from CRYPTO */
|
|
for (i = 0; i < digest_len; i++)
|
|
{
|
|
auth_iv = (dev->dump->auth_iv[i]);
|
|
|
|
*((unsigned int *)digest_ptr + i) = auth_iv;
|
|
}
|
|
|
|
return CRYPTO_ERR_NONE;
|
|
}
|
|
|
|
void crypto5_get_ctx(struct crypto_dev *dev, void *ctx_ptr)
|
|
{
|
|
((crypto_SHA1_ctx *) ctx_ptr)->auth_bytecnt[0] = BE32(dev->dump->auth_bytcnt[0]);
|
|
((crypto_SHA1_ctx *) ctx_ptr)->auth_bytecnt[1] = BE32(dev->dump->auth_bytcnt[1]);
|
|
}
|
|
|
|
uint32_t crypto5_get_max_auth_blk_size(struct crypto_dev *dev)
|
|
{
|
|
return (dev->bam.max_desc_len * (dev->bam.pipe[CRYPTO_WRITE_PIPE_INDEX].fifo.size - 2));
|
|
}
|