144 lines
3.8 KiB
C
144 lines
3.8 KiB
C
/*
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* Copyright (c) 2012, The Linux Foundation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of The Linux Foundation nor
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* the names of its contributors may be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <stdint.h>
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#include <debug.h>
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#include <reg.h>
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#include <err.h>
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#include <bits.h>
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#include <limits.h>
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#include <platform/timer.h>
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#include <clock.h>
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#include <clock_pll.h>
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/*
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* pll_vote_clk functions
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*/
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int pll_vote_clk_enable(struct clk *clk)
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{
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uint32_t ena;
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struct pll_vote_clk *pll = to_pll_vote_clk(clk);
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ena = readl_relaxed(pll->en_reg);
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ena |= pll->en_mask;
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writel_relaxed(ena, pll->en_reg);
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/* Wait until PLL is enabled */
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while ((readl_relaxed(pll->status_reg) & pll->status_mask) == 0);
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return 0;
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}
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void pll_vote_clk_disable(struct clk *clk)
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{
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uint32_t ena;
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struct pll_vote_clk *pll = to_pll_vote_clk(clk);
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ena = readl_relaxed(pll->en_reg);
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ena &= ~(pll->en_mask);
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writel_relaxed(ena, pll->en_reg);
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}
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unsigned pll_vote_clk_get_rate(struct clk *clk)
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{
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struct pll_vote_clk *pll = to_pll_vote_clk(clk);
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return pll->rate;
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}
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struct clk *pll_vote_clk_get_parent(struct clk *clk)
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{
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struct pll_vote_clk *pll = to_pll_vote_clk(clk);
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return pll->parent;
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}
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int pll_vote_clk_is_enabled(struct clk *clk)
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{
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struct pll_vote_clk *pll = to_pll_vote_clk(clk);
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return !!(readl_relaxed(pll->status_reg) & pll->status_mask);
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}
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/*
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* PLLs functions
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*/
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int pll_clk_enable(struct clk *clk)
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{
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uint32_t mode;
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struct pll_clk *pll = to_pll_clk(clk);
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mode = readl_relaxed(pll->mode_reg);
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/* Disable PLL bypass mode. */
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mode |= BIT(1);
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writel_relaxed(mode, pll->mode_reg);
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/*
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* H/W requires a 5us delay between disabling the bypass and
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* de-asserting the reset. Delay 10us just to be safe.
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*/
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udelay(10);
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/* De-assert active-low PLL reset. */
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mode |= BIT(2);
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writel_relaxed(mode, pll->mode_reg);
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/* Wait until PLL is locked. */
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udelay(50);
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/* Enable PLL output. */
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mode |= BIT(0);
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writel_relaxed(mode, pll->mode_reg);
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return 0;
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}
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void pll_clk_disable(struct clk *clk)
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{
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uint32_t mode;
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struct pll_clk *pll = to_pll_clk(clk);
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/*
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* Disable the PLL output, disable test mode, enable
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* the bypass mode, and assert the reset.
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*/
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mode = readl_relaxed(pll->mode_reg);
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mode &= ~BM(3, 0);
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writel_relaxed(mode, pll->mode_reg);
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}
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unsigned pll_clk_get_rate(struct clk *clk)
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{
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struct pll_clk *pll = to_pll_clk(clk);
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return pll->rate;
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}
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struct clk *pll_clk_get_parent(struct clk *clk)
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{
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struct pll_clk *pll = to_pll_clk(clk);
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return pll->parent;
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}
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