230 lines
6.2 KiB
C
230 lines
6.2 KiB
C
/*
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* Copyright (c) 2012, The Linux Foundation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of The Linux Foundation nor
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* the names of its contributors may be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <assert.h>
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#include <reg.h>
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#include <err.h>
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#include <clock.h>
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#include <clock_pll.h>
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#include <clock_lib2.h>
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/*=============== CXO clock ops =============*/
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int cxo_clk_enable(struct clk *clk)
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{
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/* Nothing to do. */
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return 0;
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}
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void cxo_clk_disable(struct clk *clk)
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{
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/* Nothing to do. */
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return;
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}
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/*=============== Branch clock ops =============*/
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/* Branch clock enable */
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int clock_lib2_branch_clk_enable(struct clk *clk)
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{
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int rc = 0;
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uint32_t cbcr_val;
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struct branch_clk *bclk = to_branch_clk(clk);
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cbcr_val = readl(bclk->cbcr_reg);
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cbcr_val |= CBCR_BRANCH_ENABLE_BIT;
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writel(cbcr_val, bclk->cbcr_reg);
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/* wait until status shows it is enabled */
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while(readl(bclk->cbcr_reg) & CBCR_BRANCH_OFF_BIT);
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return rc;
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}
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/* Branch clock disable */
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void clock_lib2_branch_clk_disable(struct clk *clk)
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{
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uint32_t cbcr_val;
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struct branch_clk *bclk = to_branch_clk(clk);
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cbcr_val = readl(bclk->cbcr_reg);
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cbcr_val &= ~CBCR_BRANCH_ENABLE_BIT;
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writel(cbcr_val, bclk->cbcr_reg);
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/* wait until status shows it is disabled */
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while(!(readl(bclk->cbcr_reg) & CBCR_BRANCH_OFF_BIT));
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}
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/* Branch clock set rate */
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int clock_lib2_branch_set_rate(struct clk *c, unsigned rate)
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{
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struct branch_clk *branch = to_branch_clk(c);
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if (!branch->has_sibling)
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return clk_set_rate(branch->parent, rate);
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return -1;
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}
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/*=============== Root clock ops =============*/
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/* Root enable */
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int clock_lib2_rcg_enable(struct clk *c)
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{
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/* Hardware feedback from branch enable results in root being enabled.
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* Nothing to do here.
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*/
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return 0;
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}
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/* Root set rate:
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* Find the entry in the frequecy table corresponding to the requested rate.
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* Enable the source clock required for the new frequency.
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* Call the set_rate function defined for this particular root clock.
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*/
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int clock_lib2_rcg_set_rate(struct clk *c, unsigned rate)
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{
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struct rcg_clk *rclk = to_rcg_clk(c);
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struct clk_freq_tbl *nf; /* new freq */
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int rc = 0;
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/* ck if new freq is in table */
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for (nf = rclk->freq_tbl; nf->freq_hz != FREQ_END
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&& nf->freq_hz != rate; nf++)
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;
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/* Frequency not found in the table */
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if (nf->freq_hz == FREQ_END)
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return ERR_INVALID_ARGS;
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/* Check if frequency is actually changed. */
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if (nf == rclk->current_freq)
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return rc;
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/* First enable the source clock for this freq. */
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clk_enable(nf->src_clk);
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/* Perform clock-specific frequency switch operations. */
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ASSERT(rclk->set_rate);
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rclk->set_rate(rclk, nf);
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/* update current freq */
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rclk->current_freq = nf;
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return rc;
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}
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/* root update config: informs h/w to start using the new config values */
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static void clock_lib2_rcg_update_config(struct rcg_clk *rclk)
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{
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uint32_t cmd;
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cmd = readl(rclk->cmd_reg);
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cmd |= CMD_UPDATE_BIT;
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writel(cmd, rclk->cmd_reg);
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/* Wait for frequency to be updated. */
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while(readl(rclk->cmd_reg) & CMD_UPDATE_MASK);
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}
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/* root set rate for clocks with half integer and MND divider */
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void clock_lib2_rcg_set_rate_mnd(struct rcg_clk *rclk, struct clk_freq_tbl *freq)
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{
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uint32_t cfg;
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/* Program MND values */
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writel(freq->m_val, rclk->m_reg);
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writel(freq->n_val, rclk->n_reg);
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writel(freq->d_val, rclk->d_reg);
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/* setup src select and divider */
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cfg = readl(rclk->cfg_reg);
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cfg &= ~(CFG_SRC_SEL_MASK | CFG_SRC_DIV_MASK | CFG_MODE_MASK);
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cfg |= freq->div_src_val;
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if(freq->n_val !=0)
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{
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cfg |= (CFG_MODE_DUAL_EDGE << CFG_MODE_OFFSET);
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}
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writel(cfg, rclk->cfg_reg);
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/* Inform h/w to start using the new config. */
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clock_lib2_rcg_update_config(rclk);
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}
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/* root set rate for clocks with half integer divider */
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void clock_lib2_rcg_set_rate_hid(struct rcg_clk *rclk, struct clk_freq_tbl *freq)
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{
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uint32_t cfg;
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/* setup src select and divider */
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cfg = readl(rclk->cfg_reg);
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cfg &= ~(CFG_SRC_SEL_MASK | CFG_SRC_DIV_MASK);
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cfg |= freq->div_src_val;
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writel(cfg, rclk->cfg_reg);
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clock_lib2_rcg_update_config(rclk);
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}
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/*=============== Vote clock ops =============*/
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/* Vote clock enable */
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int clock_lib2_vote_clk_enable(struct clk *c)
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{
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uint32_t vote_regval;
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uint32_t val;
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struct vote_clk *vclk = to_local_vote_clk(c);
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vote_regval = readl(vclk->vote_reg);
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vote_regval |= vclk->en_mask;
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writel_relaxed(vote_regval, vclk->vote_reg);
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do {
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val = readl(vclk->cbcr_reg);
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val &= BRANCH_CHECK_MASK;
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}
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/* wait until status shows it is enabled */
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while((val != BRANCH_ON_VAL) && (val != BRANCH_NOC_FSM_ON_VAL));
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return 0;
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}
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/* Vote clock disable */
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void clock_lib2_vote_clk_disable(struct clk *c)
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{
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uint32_t vote_regval;
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struct vote_clk *vclk = to_local_vote_clk(c);
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vote_regval = readl(vclk->vote_reg);
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vote_regval &= ~vclk->en_mask;
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writel_relaxed(vote_regval, vclk->vote_reg);
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/* wait until status shows it is disabled */
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while(!(readl(vclk->cbcr_reg) & CBCR_BRANCH_OFF_BIT));
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}
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