282 lines
6.6 KiB
C
282 lines
6.6 KiB
C
/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of The Linux Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <err.h>
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#include <assert.h>
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#include <debug.h>
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#include <reg.h>
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#include <platform/timer.h>
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#include <platform/iomap.h>
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#include <mmc.h>
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#include <clock.h>
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#include <platform/clock.h>
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void hsusb_clock_init(void)
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{
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int ret;
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struct clk *iclk, *cclk;
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ret = clk_get_set_enable("usb_iface_clk", 0, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set usb_iface_clk ret = %d\n", ret);
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ASSERT(0);
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}
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ret = clk_get_set_enable("usb_core_clk", 75000000, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set usb_core_clk ret = %d\n", ret);
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ASSERT(0);
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}
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mdelay(20);
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iclk = clk_get("usb_iface_clk");
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cclk = clk_get("usb_core_clk");
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clk_disable(iclk);
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clk_disable(cclk);
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mdelay(20);
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/* Start the block reset for usb */
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writel(1, USB_HS_BCR);
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mdelay(20);
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/* Take usb block out of reset */
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writel(0, USB_HS_BCR);
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mdelay(20);
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ret = clk_enable(iclk);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret);
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ASSERT(0);
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}
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ret = clk_enable(cclk);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret);
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ASSERT(0);
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}
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}
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void clock_init_mmc(uint32_t interface)
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{
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char clk_name[64];
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int ret;
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snprintf(clk_name, 64, "sdc%u_iface_clk", interface);
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/* enable interface clock */
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ret = clk_get_set_enable(clk_name, 0, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set sdc1_iface_clk ret = %d\n", ret);
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ASSERT(0);
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}
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}
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/* Configure MMC clock */
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void clock_config_mmc(uint32_t interface, uint32_t freq)
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{
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int ret;
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uint32_t reg;
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char clk_name[64];
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snprintf(clk_name, 64, "sdc%u_core_clk", interface);
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if(freq == MMC_CLK_400KHZ)
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{
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ret = clk_get_set_enable(clk_name, 400000, 1);
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}
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else if(freq == MMC_CLK_50MHZ)
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{
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ret = clk_get_set_enable(clk_name, 50000000, 1);
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}
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else if(freq == MMC_CLK_200MHZ)
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{
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ret = clk_get_set_enable(clk_name, 200000000, 1);
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}
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else
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{
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dprintf(CRITICAL, "sdc frequency (%d) is not supported\n", freq);
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ASSERT(0);
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}
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if(ret)
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{
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dprintf(CRITICAL, "failed to set sdc1_core_clk ret = %d\n", ret);
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ASSERT(0);
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}
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}
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/* Configure UART clock based on the UART block id*/
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void clock_config_uart_dm(uint8_t id)
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{
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int ret;
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ret = clk_get_set_enable("uart3_iface_clk", 0, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set uart3_iface_clk ret = %d\n", ret);
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ASSERT(0);
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}
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ret = clk_get_set_enable("uart3_core_clk", 7372800, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set uart3_core_clk ret = %d\n", ret);
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ASSERT(0);
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}
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}
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/* Function to asynchronously reset CE.
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* Function assumes that all the CE clocks are off.
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*/
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static void ce_async_reset(uint8_t instance)
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{
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if (instance == 1)
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{
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/* Start the block reset for CE */
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writel(1, GCC_CE1_BCR);
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udelay(2);
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/* Take CE block out of reset */
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writel(0, GCC_CE1_BCR);
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udelay(2);
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}
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else
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{
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dprintf(CRITICAL, "CE instance not supported instance = %d", instance);
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ASSERT(0);
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}
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}
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void clock_ce_enable(uint8_t instance)
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{
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int ret;
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char clk_name[64];
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snprintf(clk_name, 64, "ce%u_src_clk", instance);
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ret = clk_get_set_enable(clk_name, 100000000, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set ce_src_clk ret = %d\n", ret);
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ASSERT(0);
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}
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snprintf(clk_name, 64, "ce%u_core_clk", instance);
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ret = clk_get_set_enable(clk_name, 0, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set ce_core_clk ret = %d\n", ret);
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ASSERT(0);
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}
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snprintf(clk_name, 64, "ce%u_ahb_clk", instance);
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ret = clk_get_set_enable(clk_name, 0, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set ce_ahb_clk ret = %d\n", ret);
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ASSERT(0);
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}
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snprintf(clk_name, 64, "ce%u_axi_clk", instance);
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ret = clk_get_set_enable(clk_name, 0, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set ce_axi_clk ret = %d\n", ret);
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ASSERT(0);
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}
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/* Wait for 48 * #pipes cycles.
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* This is necessary as immediately after an access control reset (boot up)
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* or a debug re-enable, the Crypto core sequentially clears its internal
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* pipe key storage memory. If pipe key initialization writes are attempted
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* during this time, they may be overwritten by the internal clearing logic.
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*/
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udelay(1);
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}
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void clock_ce_disable(uint8_t instance)
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{
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struct clk *ahb_clk;
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struct clk *cclk;
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struct clk *axi_clk;
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struct clk *src_clk;
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char clk_name[64];
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snprintf(clk_name, 64, "ce%u_src_clk", instance);
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src_clk = clk_get(clk_name);
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snprintf(clk_name, 64, "ce%u_ahb_clk", instance);
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ahb_clk = clk_get(clk_name);
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snprintf(clk_name, 64, "ce%u_axi_clk", instance);
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axi_clk = clk_get(clk_name);
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snprintf(clk_name, 64, "ce%u_core_clk", instance);
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cclk = clk_get(clk_name);
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clk_disable(ahb_clk);
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clk_disable(axi_clk);
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clk_disable(cclk);
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clk_disable(src_clk);
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/* Some delay for the clocks to stabalize. */
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udelay(1);
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}
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void clock_config_ce(uint8_t instance)
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{
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/* Need to enable the clock before disabling since the clk_disable()
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* has a check to default to nop when the clk_enable() is not called
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* on that particular clock.
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*/
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clock_ce_enable(instance);
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clock_ce_disable(instance);
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ce_async_reset(instance);
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clock_ce_enable(instance);
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}
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