228 lines
7.2 KiB
C
228 lines
7.2 KiB
C
/*
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* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __MDM_CLOCKS_9607_HWIO_H
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#define __MDM_CLOCKS_9607_HWIO_H
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#define GPLL0_MODE 0x21000
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#define GPLL0_STATUS 0x21024
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#define GPLL1_MODE 0x20000
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#define GPLL1_STATUS 0x2001C
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#define GPLL2_MODE 0x25000
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#define GPLL2_STATUS 0x25024
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#define APCS_GPLL_ENA_VOTE 0x45000
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#define APCS_MODE 0x00018
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#define APSS_AHB_CMD_RCGR 0x46000
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#define PRNG_AHB_CBCR 0x13004
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#define EMAC_0_125M_CMD_RCGR 0x4E028
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#define BLSP1_QUP1_I2C_APPS_CMD_RCGR 0x200C
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#define BLSP1_QUP1_SPI_APPS_CMD_RCGR 0x2024
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#define BLSP1_QUP2_I2C_APPS_CMD_RCGR 0x3000
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#define BLSP1_QUP2_SPI_APPS_CMD_RCGR 0x3014
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#define BLSP1_QUP3_I2C_APPS_CMD_RCGR 0x4000
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#define BLSP1_QUP3_SPI_APPS_CMD_RCGR 0x4024
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#define BLSP1_QUP4_I2C_APPS_CMD_RCGR 0x5000
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#define BLSP1_QUP4_SPI_APPS_CMD_RCGR 0x5024
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#define BLSP1_QUP5_I2C_APPS_CMD_RCGR 0x6000
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#define BLSP1_QUP5_SPI_APPS_CMD_RCGR 0x6024
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#define BLSP1_QUP6_I2C_APPS_CMD_RCGR 0x7000
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#define BLSP1_QUP6_SPI_APPS_CMD_RCGR 0x7024
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#define BLSP1_UART1_APPS_CMD_RCGR 0x2044
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#define BLSP1_UART2_APPS_CMD_RCGR 0x3034
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#define BLSP1_UART3_APPS_CMD_RCGR 0x4044
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#define BLSP1_UART4_APPS_CMD_RCGR 0x5044
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#define BLSP1_UART5_APPS_CMD_RCGR 0x6044
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#define BLSP1_UART6_APPS_CMD_RCGR 0x7044
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#define CRYPTO_CMD_RCGR 0x16004
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#define GP1_CMD_RCGR 0x8004
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#define GP2_CMD_RCGR 0x9004
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#define GP3_CMD_RCGR 0xA004
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#define PDM2_CMD_RCGR 0x44010
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#define QPIC_CMD_RCGR 0x3F004
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#define SDCC1_APPS_CMD_RCGR 0x42004
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#define SDCC2_APPS_CMD_RCGR 0x43004
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#define EMAC_0_SYS_25M_CMD_RCGR 0x4E03C
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#define EMAC_0_TX_CMD_RCGR 0x4E014
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#define USB_HS_SYSTEM_CMD_RCGR 0x41010
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#define USB_HSIC_CMD_RCGR 0x3D018
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#define USB_HSIC_IO_CAL_CMD_RCGR 0x3D030
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#define USB_HSIC_SYSTEM_CMD_RCGR 0x3D000
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#define BIMC_PCNOC_AXI_CBCR 0x31024
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#define BLSP1_AHB_CBCR 0x1008
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#define APCS_CLOCK_BRANCH_ENA_VOTE 0x45004
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#define BLSP1_QUP1_I2C_APPS_CBCR 0x2008
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#define BLSP1_QUP1_SPI_APPS_CBCR 0x2004
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#define BLSP1_QUP2_I2C_APPS_CBCR 0x3010
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#define BLSP1_QUP2_SPI_APPS_CBCR 0x300C
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#define BLSP1_QUP3_I2C_APPS_CBCR 0x4020
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#define BLSP1_QUP3_SPI_APPS_CBCR 0x401C
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#define BLSP1_QUP4_I2C_APPS_CBCR 0x5020
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#define BLSP1_QUP4_SPI_APPS_CBCR 0x501C
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#define BLSP1_QUP5_I2C_APPS_CBCR 0x6020
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#define BLSP1_QUP5_SPI_APPS_CBCR 0x601C
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#define BLSP1_QUP6_I2C_APPS_CBCR 0x7020
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#define BLSP1_QUP6_SPI_APPS_CBCR 0x701C
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#define BLSP1_UART1_APPS_CBCR 0x203C
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#define BLSP1_UART2_APPS_CBCR 0x302C
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#define BLSP1_UART3_APPS_CBCR 0x403C
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#define BLSP1_UART4_APPS_CBCR 0x503C
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#define BLSP1_UART5_APPS_CBCR 0x603C
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#define BLSP1_UART6_APPS_CBCR 0x703C
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#define APSS_AHB_CBCR 0x4601C
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#define APSS_AXI_CBCR 0x46020
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#define BOOT_ROM_AHB_CBCR 0x1300C
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#define CRYPTO_AHB_CBCR 0x16024
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#define CRYPTO_AXI_CBCR 0x16020
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#define CRYPTO_CBCR 0x1601C
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#define GP1_CBCR 0x8000
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#define GP2_CBCR 0x9000
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#define GP3_CBCR 0xA000
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#define MSS_CFG_AHB_CBCR 0x49000
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#define MSS_Q6_BIMC_AXI_CBCR 0x49004
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#define PCNOC_APSS_AHB_CBCR 0x27030
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#define PDM2_CBCR 0x4400C
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#define PDM_AHB_CBCR 0x44004
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#define QPIC_AHB_CBCR 0x3F01C
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#define QPIC_CBCR 0x3F018
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#define QPIC_SYSTEM_CBCR 0x3F020
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#define SDCC1_AHB_CBCR 0x4201C
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#define SDCC1_APPS_CBCR 0x42018
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#define SDCC2_AHB_CBCR 0x4301C
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#define SDCC2_APPS_CBCR 0x43018
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#define EMAC_0_125M_CBCR 0x4E010
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#define EMAC_0_AHB_CBCR 0x4E000
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#define EMAC_0_AXI_CBCR 0x4E008
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#define EMAC_0_RX_CBCR 0x4E030
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#define EMAC_0_SYS_25M_CBCR 0x4E038
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#define EMAC_0_SYS_CBCR 0x4E034
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#define EMAC_0_TX_CBCR 0x4E00C
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#define APSS_TCU_CBCR 0x12018
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#define SMMU_CFG_CBCR 0x12038
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#define QDSS_DAP_CBCR 0x29084
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#define APCS_SMMU_CLOCK_BRANCH_ENA_VOTE 0x4500C
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#define USB2A_PHY_SLEEP_CBCR 0x4102C
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#define USB_HS_PHY_CFG_AHB_CBCR 0x41030
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#define USB_HS_AHB_CBCR 0x41008
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#define USB_HS_SYSTEM_CBCR 0x41004
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#define USB_HS_BCR 0x41000
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#define USB_HSIC_AHB_CBCR 0x3D04C
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#define USB_HSIC_CBCR 0x3D050
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#define USB_HSIC_IO_CAL_CBCR 0x3D054
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#define USB_HSIC_IO_CAL_SLEEP_CBCR 0x3D058
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#define USB_HSIC_SYSTEM_CBCR 0x3D048
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#define USB_HS_HSIC_BCR 0x3D05C
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#define USB2_HS_PHY_ONLY_BCR 0x41034
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#define QUSB2_PHY_BCR 0x4103C
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#define GCC_DEBUG_CLK_CTL 0x74000
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#define CLOCK_FRQ_MEASURE_CTL 0x74004
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#define CLOCK_FRQ_MEASURE_STATUS 0x74008
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#define PLLTEST_PAD_CFG 0x7400C
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#define GCC_XO_DIV4_CBCR 0x30034
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#define xo_source_val 0
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#define xo_a_source_val 0
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#define gpll0_source_val 1
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#define gpll2_source_val 1
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#define emac_0_125m_clk_source_val 1
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#define emac_0_tx_clk_source_val 2
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#define F(f, s, div, m, n) \
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{ \
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.freq_hz = (f), \
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.src_clk = &s##_clk_src.c, \
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.m_val = (m), \
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.n_val = ~((n)-(m)) * !!(n), \
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.d_val = ~(n),\
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.div_src_val = BVAL(4, 0, (int)(2*(div) - 1)) \
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| BVAL(10, 8, s##_source_val), \
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}
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#define F_EXT(f, s, div, m, n) \
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{ \
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.freq_hz = (f), \
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.m_val = (m), \
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.n_val = ~((n)-(m)) * !!(n), \
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.d_val = ~(n),\
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.div_src_val = BVAL(4, 0, (int)(2*(div) - 1)) \
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| BVAL(10, 8, s##_source_val), \
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}
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#define VDD_DIG_FMAX_MAP1(l1, f1) \
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.vdd_class = &vdd_dig, \
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.fmax = (unsigned long[VDD_DIG_NUM]) { \
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[VDD_DIG_##l1] = (f1), \
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}, \
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.num_fmax = VDD_DIG_NUM
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#define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \
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.vdd_class = &vdd_dig, \
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.fmax = (unsigned long[VDD_DIG_NUM]) { \
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[VDD_DIG_##l1] = (f1), \
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[VDD_DIG_##l2] = (f2), \
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}, \
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.num_fmax = VDD_DIG_NUM
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#define VDD_DIG_FMAX_MAP3(l1, f1, l2, f2, l3, f3) \
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.vdd_class = &vdd_dig, \
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.fmax = (unsigned long[VDD_DIG_NUM]) { \
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[VDD_DIG_##l1] = (f1), \
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[VDD_DIG_##l2] = (f2), \
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[VDD_DIG_##l3] = (f3), \
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}, \
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.num_fmax = VDD_DIG_NUM
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enum vdd_dig_levels {
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VDD_DIG_NONE,
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VDD_DIG_LOWER,
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VDD_DIG_LOW,
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VDD_DIG_NOMINAL,
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VDD_DIG_HIGH,
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VDD_DIG_NUM
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};
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static int vdd_corner[] = {
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RPM_REGULATOR_LEVEL_NONE, /* VDD_DIG_NONE */
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RPM_REGULATOR_LEVEL_SVS, /* VDD_DIG_LOWER */
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RPM_REGULATOR_LEVEL_SVS_PLUS, /*VDD_DIG_LOW*/
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RPM_REGULATOR_LEVEL_NOM, /* VDD_DIG_NOMINAL */
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RPM_REGULATOR_LEVEL_TURBO, /* VDD_DIG_HIGH */
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};
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static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner, NULL);
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#define VDD_STROMER_FMAX_MAP1(l1, f1) \
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.vdd_class = &vdd_stromer_pll, \
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.fmax = (unsigned long[VDD_DIG_NUM]) { \
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[VDD_DIG_##l1] = (f1), \
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}, \
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.num_fmax = VDD_DIG_NUM
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#define RPM_MISC_CLK_TYPE 0x306b6c63
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#define RPM_BUS_CLK_TYPE 0x316b6c63
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#define RPM_MEM_CLK_TYPE 0x326b6c63
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#define RPM_SMD_KEY_ENABLE 0x62616E45
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#define RPM_QPIC_CLK_TYPE 0x63697071
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#define XO_ID 0x0
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#define QDSS_ID 0x1
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#define PCNOC_ID 0x0
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#define BIMC_ID 0x0
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#define QPIC_ID 0x0
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/* XO clock */
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#define BB_CLK1_ID 1
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#define RF_CLK2_ID 5
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#endif
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