1055 lines
29 KiB
C
1055 lines
29 KiB
C
/* Copyright (c) 2008-2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef MDSS_PANEL_H
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#define MDSS_PANEL_H
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/stringify.h>
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#include <linux/types.h>
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#include <linux/debugfs.h>
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/* panel id type */
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struct panel_id {
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u16 id;
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u16 type;
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};
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#define DEFAULT_FRAME_RATE 60
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#define DEFAULT_ROTATOR_FRAME_RATE 120
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#define ROTATOR_LOW_FRAME_RATE 30
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#define MDSS_DSI_RST_SEQ_LEN 10
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/* worst case prefill lines for all chipsets including all vertical blank */
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#define MDSS_MDP_MAX_PREFILL_FETCH 25
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#define OVERRIDE_CFG "override"
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#define SIM_PANEL "sim"
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#define SIM_SW_TE_PANEL "sim-swte"
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#define SIM_HW_TE_PANEL "sim-hwte"
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/* panel type list */
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#define NO_PANEL 0xffff /* No Panel */
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#define MDDI_PANEL 1 /* MDDI */
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#define EBI2_PANEL 2 /* EBI2 */
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#define LCDC_PANEL 3 /* internal LCDC type */
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#define EXT_MDDI_PANEL 4 /* Ext.MDDI */
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#define TV_PANEL 5 /* TV */
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#define HDMI_PANEL 6 /* HDMI TV */
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#define DTV_PANEL 7 /* DTV */
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#define MIPI_VIDEO_PANEL 8 /* MIPI */
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#define MIPI_CMD_PANEL 9 /* MIPI */
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#define WRITEBACK_PANEL 10 /* Wifi display */
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#define LVDS_PANEL 11 /* LVDS */
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#define EDP_PANEL 12 /* LVDS */
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#define DSC_PPS_LEN 128
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static inline const char *mdss_panel2str(u32 panel)
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{
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static const char const *names[] = {
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#define PANEL_NAME(n) [n ## _PANEL] = __stringify(n)
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PANEL_NAME(MIPI_VIDEO),
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PANEL_NAME(MIPI_CMD),
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PANEL_NAME(EDP),
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PANEL_NAME(HDMI),
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PANEL_NAME(DTV),
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PANEL_NAME(WRITEBACK),
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#undef PANEL_NAME
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};
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if (panel >= ARRAY_SIZE(names) || !names[panel])
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return "UNKNOWN";
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return names[panel];
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}
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/* panel class */
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enum {
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DISPLAY_LCD = 0, /* lcd = ebi2/mddi */
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DISPLAY_LCDC, /* lcdc */
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DISPLAY_TV, /* TV Out */
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DISPLAY_EXT_MDDI, /* External MDDI */
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DISPLAY_WRITEBACK,
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};
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/* panel device locaiton */
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enum {
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DISPLAY_1 = 0, /* attached as first device */
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DISPLAY_2, /* attached on second device */
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DISPLAY_3, /* attached on third device */
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DISPLAY_4, /* attached on fourth device */
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MAX_PHYS_TARGET_NUM,
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};
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enum {
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MDSS_PANEL_INTF_INVALID = -1,
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MDSS_PANEL_INTF_DSI,
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MDSS_PANEL_INTF_EDP,
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MDSS_PANEL_INTF_HDMI,
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};
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enum {
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MDSS_PANEL_POWER_OFF = 0,
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MDSS_PANEL_POWER_ON,
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MDSS_PANEL_POWER_LP1,
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MDSS_PANEL_POWER_LP2,
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};
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enum {
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MDSS_PANEL_BLANK_BLANK = 0,
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MDSS_PANEL_BLANK_UNBLANK,
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MDSS_PANEL_BLANK_LOW_POWER,
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};
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enum {
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MODE_GPIO_NOT_VALID = 0,
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MODE_GPIO_HIGH,
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MODE_GPIO_LOW,
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};
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/*
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* enum sim_panel_modes - Different panel modes for simulator panels
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*
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* @SIM_MODE: Disables all host reads for video mode simulator panels.
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* @SIM_SW_TE_MODE: Disables all host reads and genereates the SW TE. Used
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* for cmd mode simulator panels.
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* @SIM_HW_TE_MODE: Disables all host reads and expects TE from hardware
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* (terminator card). Used for cmd mode simulator panels.
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*/
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enum {
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SIM_MODE = 1,
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SIM_SW_TE_MODE,
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SIM_HW_TE_MODE,
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};
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struct mdss_rect {
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u16 x;
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u16 y;
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u16 w;
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u16 h;
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};
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#define MDSS_MAX_PANEL_LEN 256
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#define MDSS_INTF_MAX_NAME_LEN 5
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#define MDSS_DISPLAY_ID_MAX_LEN 16
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struct mdss_panel_intf {
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char name[MDSS_INTF_MAX_NAME_LEN];
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int type;
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};
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struct mdss_panel_cfg {
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char arg_cfg[MDSS_MAX_PANEL_LEN + 1];
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int pan_intf;
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bool lk_cfg;
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bool init_done;
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};
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#define MDP_INTF_DSI_CMD_FIFO_UNDERFLOW 0x0001
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#define MDP_INTF_DSI_VIDEO_FIFO_OVERFLOW 0x0002
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struct mdss_intf_recovery {
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void (*fxn)(void *ctx, int event);
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void *data;
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};
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/**
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* enum mdss_intf_events - Different events generated by MDP core
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*
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* @MDSS_EVENT_RESET: MDP control path is being (re)initialized.
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* @MDSS_EVENT_LINK_READY Interface data path inited to ready state.
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* @MDSS_EVENT_UNBLANK: Sent before first frame update from MDP is
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* sent to panel.
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* @MDSS_EVENT_PANEL_ON: After first frame update from MDP.
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* @MDSS_EVENT_POST_PANEL_ON send 2nd phase panel on commands to panel
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* @MDSS_EVENT_BLANK: MDP has no contents to display only blank screen
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* is shown in panel. Sent before panel off.
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* @MDSS_EVENT_PANEL_OFF: MDP has suspended frame updates, panel should be
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* completely shutdown after this call.
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* @MDSS_EVENT_CLOSE: MDP has tore down entire session.
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* @MDSS_EVENT_SUSPEND: Propagation of power suspend event.
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* @MDSS_EVENT_RESUME: Propagation of power resume event.
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* @MDSS_EVENT_CHECK_PARAMS: Event generated when a panel reconfiguration is
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* requested including when resolution changes.
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* The event handler receives pointer to
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* struct mdss_panel_info and should return one of:
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* - negative if the configuration is invalid
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* - 0 if there is no panel reconfig needed
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* - 1 if reconfig is needed to take effect
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* @MDSS_EVENT_CONT_SPLASH_BEGIN: Special event used to handle transition of
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* display state from boot loader to panel driver.
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* The event handler will disable the panel.
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* @MDSS_EVENT_CONT_SPLASH_FINISH: Special event used to handle transition of
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* display state from boot loader to panel driver.
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* The event handler will enable the panel and
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* vote for the display clocks.
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* @MDSS_EVENT_PANEL_UPDATE_FPS: Event to update the frame rate of the panel.
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* @MDSS_EVENT_FB_REGISTERED: Called after fb dev driver has been registered,
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* panel driver gets ptr to struct fb_info which
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* holds fb dev information.
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* @MDSS_EVENT_PANEL_CLK_CTRL: panel clock control
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* - 0 clock disable
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* - 1 clock enable
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* @MDSS_EVENT_DSI_CMDLIST_KOFF: acquire dsi_mdp_busy lock before kickoff.
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* @MDSS_EVENT_ENABLE_PARTIAL_ROI: Event to update ROI of the panel.
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* @MDSS_EVENT_DSC_PPS_SEND: Event to send DSC PPS command to panel.
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* @MDSS_EVENT_DSI_STREAM_SIZE: Event to update DSI controller's stream size
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* @MDSS_EVENT_DSI_UPDATE_PANEL_DATA: Event to update the dsi driver structures
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* based on the dsi mode passed as argument.
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* - 0: update to video mode
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* - 1: update to command mode
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* @MDSS_EVENT_REGISTER_RECOVERY_HANDLER: Event to recover the interface in
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* case there was any errors detected.
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* @MDSS_EVENT_DSI_PANEL_STATUS: Event to check the panel status
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* <= 0: panel check fail
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* > 0: panel check success
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* @MDSS_EVENT_DSI_DYNAMIC_SWITCH: Send DCS command to panel to initiate
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* switching panel to new mode
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* - MIPI_VIDEO_PANEL: switch to video mode
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* - MIPI_CMD_PANEL: switch to command mode
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* @MDSS_EVENT_DSI_RECONFIG_CMD: Setup DSI controller in new mode
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* - MIPI_VIDEO_PANEL: switch to video mode
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* - MIPI_CMD_PANEL: switch to command mode
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* @MDSS_EVENT_DSI_RESET_WRITE_PTR: Reset the write pointer coordinates on
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* the panel.
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* @MDSS_EVENT_PANEL_TIMING_SWITCH: Panel timing switch is requested.
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* Argument provided is new panel timing.
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*/
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enum mdss_intf_events {
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MDSS_EVENT_RESET = 1,
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MDSS_EVENT_LINK_READY,
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MDSS_EVENT_UNBLANK,
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MDSS_EVENT_PANEL_ON,
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MDSS_EVENT_POST_PANEL_ON,
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MDSS_EVENT_BLANK,
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MDSS_EVENT_PANEL_OFF,
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MDSS_EVENT_CLOSE,
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MDSS_EVENT_SUSPEND,
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MDSS_EVENT_RESUME,
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MDSS_EVENT_CHECK_PARAMS,
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MDSS_EVENT_CONT_SPLASH_BEGIN,
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MDSS_EVENT_CONT_SPLASH_FINISH,
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MDSS_EVENT_PANEL_UPDATE_FPS,
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MDSS_EVENT_FB_REGISTERED,
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MDSS_EVENT_PANEL_CLK_CTRL,
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MDSS_EVENT_DSI_CMDLIST_KOFF,
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MDSS_EVENT_ENABLE_PARTIAL_ROI,
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MDSS_EVENT_DSC_PPS_SEND,
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MDSS_EVENT_DSI_STREAM_SIZE,
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MDSS_EVENT_DSI_UPDATE_PANEL_DATA,
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MDSS_EVENT_REGISTER_RECOVERY_HANDLER,
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MDSS_EVENT_DSI_PANEL_STATUS,
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MDSS_EVENT_DSI_DYNAMIC_SWITCH,
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MDSS_EVENT_DSI_RECONFIG_CMD,
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MDSS_EVENT_DSI_RESET_WRITE_PTR,
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MDSS_EVENT_PANEL_TIMING_SWITCH,
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};
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struct lcd_panel_info {
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u32 h_back_porch;
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u32 h_front_porch;
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u32 h_pulse_width;
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u32 v_back_porch;
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u32 v_front_porch;
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u32 v_pulse_width;
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u32 border_clr;
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u32 underflow_clr;
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u32 hsync_skew;
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u32 border_top;
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u32 border_bottom;
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u32 border_left;
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u32 border_right;
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/* Pad width */
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u32 xres_pad;
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/* Pad height */
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u32 yres_pad;
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};
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/* DSI PHY configuration */
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struct mdss_dsi_phy_ctrl {
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char regulator[7]; /* 8996, 1 * 5 */
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char timing[12];
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char ctrl[4];
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char strength[10]; /* 8996, 2 * 5 */
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char bistctrl[6];
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uint32_t pll[21];
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char lanecfg[45]; /* 8996, 4 * 5 */
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bool reg_ldo_mode;
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char timing_8996[40];/* 8996, 8 * 5 */
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char regulator_len;
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char strength_len;
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char lanecfg_len;
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};
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/**
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* enum dynamic_mode_switch - Dynamic mode switch methods
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* @DYNAMIC_MODE_SWITCH_DISABLED: Dynamic mode switch is not supported
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* @DYNAMIC_MODE_SWITCH_SUSPEND_RESUME: Switch requires panel suspend/resume
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* @DYNAMIC_MODE_SWITCH_IMMEDIATE: Supports video/cmd mode switch immediately
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* @DYNAMIC_MODE_RESOLUTION_SWITCH_IMMEDIATE: Panel supports display resolution
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* switch immediately.
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**/
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enum dynamic_mode_switch {
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DYNAMIC_MODE_SWITCH_DISABLED = 0,
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DYNAMIC_MODE_SWITCH_SUSPEND_RESUME,
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DYNAMIC_MODE_SWITCH_IMMEDIATE,
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DYNAMIC_MODE_RESOLUTION_SWITCH_IMMEDIATE,
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};
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/**
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* enum dynamic_switch_modes - Type of dynamic mode switch to be given as
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* argument to MDSS_EVENT_DSI_DYNAMIC_SWITCH event
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* @SWITCH_TO_CMD_MODE: Switch from DSI video mode to command mode
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* @SWITCH_TO_VIDEO_MODE: Switch from DSI command mode to video mode
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* @SWITCH_RESOLUTION: Switch only display resolution
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**/
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enum dynamic_switch_modes {
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SWITCH_MODE_UNKNOWN = 0,
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SWITCH_TO_CMD_MODE,
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SWITCH_TO_VIDEO_MODE,
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SWITCH_RESOLUTION,
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};
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/**
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* struct mdss_panel_timing - structure for panel timing information
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* @list: List head ptr to track within panel data timings list
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* @name: A unique name of this timing that can be used to identify it
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* @xres: Panel width
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* @yres: Panel height
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* @h_back_porch: Horizontal back porch
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* @h_front_porch: Horizontal front porch
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* @h_pulse_width: Horizontal pulse width
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* @hsync_skew: Horizontal sync skew
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* @v_back_porch: Vertical back porch
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* @v_front_porch: Vertical front porch
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* @v_pulse_width: Vertical pulse width
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* @border_top: Border color on top
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* @border_bottom: Border color on bottom
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* @border_left: Border color on left
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* @border_right: Border color on right
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* @clk_rate: Pixel clock rate of this panel timing
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* @frame_rate: Display refresh rate
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* @fbc: Framebuffer compression parameters for this display timing
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* @te: Tearcheck parameters for this display timing
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**/
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struct mipi_panel_info {
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char boot_mode; /* identify if mode switched from starting mode */
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char mode; /* video/cmd */
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char interleave_mode;
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char crc_check;
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char ecc_check;
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char dst_format; /* shared by video and command */
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char data_lane0;
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char data_lane1;
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char data_lane2;
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char data_lane3;
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char rgb_swap;
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char b_sel;
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char g_sel;
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char r_sel;
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char rx_eot_ignore;
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char tx_eot_append;
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char t_clk_post; /* 0xc0, DSI_CLKOUT_TIMING_CTRL */
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char t_clk_pre; /* 0xc0, DSI_CLKOUT_TIMING_CTRL */
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char vc; /* virtual channel */
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struct mdss_dsi_phy_ctrl dsi_phy_db;
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/* video mode */
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char pulse_mode_hsa_he;
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char hfp_power_stop;
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char hbp_power_stop;
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char hsa_power_stop;
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char eof_bllp_power_stop;
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char last_line_interleave_en;
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char bllp_power_stop;
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char traffic_mode;
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char frame_rate;
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/* command mode */
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char interleave_max;
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char insert_dcs_cmd;
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char wr_mem_continue;
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char wr_mem_start;
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char te_sel;
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char stream; /* 0 or 1 */
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char mdp_trigger;
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char dma_trigger;
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/* Dynamic Switch Support */
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enum dynamic_mode_switch dms_mode;
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u32 pixel_packing;
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u32 dsi_pclk_rate;
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/* The packet-size should not bet changed */
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char no_max_pkt_size;
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/* Clock required during LP commands */
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bool force_clk_lane_hs;
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char vsync_enable;
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char hw_vsync_mode;
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char lp11_init;
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u32 init_delay;
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};
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struct edp_panel_info {
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char frame_rate; /* fps */
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};
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enum dynamic_fps_update {
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DFPS_SUSPEND_RESUME_MODE,
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DFPS_IMMEDIATE_CLK_UPDATE_MODE,
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DFPS_IMMEDIATE_PORCH_UPDATE_MODE_VFP,
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DFPS_IMMEDIATE_PORCH_UPDATE_MODE_HFP,
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DFPS_MODE_MAX
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};
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enum lvds_mode {
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LVDS_SINGLE_CHANNEL_MODE,
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LVDS_DUAL_CHANNEL_MODE,
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};
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struct lvds_panel_info {
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enum lvds_mode channel_mode;
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/* Channel swap in dual mode */
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char channel_swap;
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};
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enum {
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COMPRESSION_NONE,
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COMPRESSION_DSC,
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COMPRESSION_FBC
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};
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struct dsc_desc {
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/*
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* Following parameters can change per frame if partial update is on
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*/
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int pic_height;
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int pic_width;
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int initial_lines;
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/*
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* Following parameters are used for DSI and not for MDP. They can
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* change per frame if partial update is enabled.
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*/
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int pkt_per_line;
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int bytes_in_slice;
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int bytes_per_pkt;
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int eol_byte_num;
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int pclk_per_line; /* width */
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/*
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* Following parameters only changes when slice dimensions are changed.
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*/
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int full_frame_slices; /* denotes number of slice per intf */
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int slice_height;
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int slice_width;
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int chunk_size;
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int slice_last_group_size;
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int bpp; /* target bits per pixel */
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int bpc; /* uncompressed bits per component */
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int line_buf_depth;
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bool config_by_manufacture_cmd;
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bool block_pred_enable;
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int vbr_enable;
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int enable_422;
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int convert_rgb;
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int input_10_bits;
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int slice_per_pkt;
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int initial_dec_delay;
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int initial_xmit_delay;
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int initial_scale_value;
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int scale_decrement_interval;
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int scale_increment_interval;
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int first_line_bpg_offset;
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int nfl_bpg_offset;
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int slice_bpg_offset;
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int initial_offset;
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int final_offset;
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int rc_model_size; /* rate_buffer_size */
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int det_thresh_flatness;
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int max_qp_flatness;
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int min_qp_flatness;
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int edge_factor;
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int quant_incr_limit0;
|
|
int quant_incr_limit1;
|
|
int tgt_offset_hi;
|
|
int tgt_offset_lo;
|
|
u32 *buf_thresh;
|
|
char *range_min_qp;
|
|
char *range_max_qp;
|
|
char *range_bpg_offset;
|
|
};
|
|
|
|
struct fbc_panel_info {
|
|
u32 enabled;
|
|
u32 target_bpp;
|
|
u32 comp_mode;
|
|
u32 qerr_enable;
|
|
u32 cd_bias;
|
|
u32 pat_enable;
|
|
u32 vlc_enable;
|
|
u32 bflc_enable;
|
|
|
|
u32 line_x_budget;
|
|
u32 block_x_budget;
|
|
u32 block_budget;
|
|
|
|
u32 lossless_mode_thd;
|
|
u32 lossy_mode_thd;
|
|
u32 lossy_rgb_thd;
|
|
u32 lossy_mode_idx;
|
|
|
|
u32 slice_height;
|
|
bool pred_mode;
|
|
bool enc_mode;
|
|
u32 max_pred_err;
|
|
};
|
|
|
|
struct mdss_mdp_pp_tear_check {
|
|
u32 tear_check_en;
|
|
u32 sync_cfg_height;
|
|
u32 vsync_init_val;
|
|
u32 sync_threshold_start;
|
|
u32 sync_threshold_continue;
|
|
u32 start_pos;
|
|
u32 rd_ptr_irq;
|
|
u32 refx100;
|
|
};
|
|
|
|
struct mdss_panel_info {
|
|
u32 xres;
|
|
u32 yres;
|
|
u32 physical_width;
|
|
u32 physical_height;
|
|
u32 bpp;
|
|
u32 type;
|
|
u32 wait_cycle;
|
|
u32 pdest;
|
|
u32 brightness_max;
|
|
u32 bl_max;
|
|
u32 bl_min;
|
|
u32 fb_num;
|
|
u64 clk_rate;
|
|
u32 clk_min;
|
|
u64 clk_max;
|
|
u32 mdp_transfer_time_us;
|
|
u32 frame_count;
|
|
u32 is_3d_panel;
|
|
u32 out_format;
|
|
u32 rst_seq[MDSS_DSI_RST_SEQ_LEN];
|
|
u32 rst_seq_len;
|
|
u32 vic; /* video identification code */
|
|
struct mdss_rect roi;
|
|
int pwm_pmic_gpio;
|
|
int pwm_lpg_chan;
|
|
int pwm_period;
|
|
bool dynamic_fps;
|
|
bool ulps_feature_enabled;
|
|
bool ulps_suspend_enabled;
|
|
bool panel_ack_disabled;
|
|
bool esd_check_enabled;
|
|
char dfps_update;
|
|
/* new requested fps before it is updated in hw */
|
|
int new_fps;
|
|
/* stores initial fps after boot */
|
|
u32 default_fps;
|
|
/* stores initial vtotal (vfp-method) or htotal (hfp-method) */
|
|
u32 saved_total;
|
|
/* stores initial vfp (vfp-method) or hfp (hfp-method) */
|
|
u32 saved_fporch;
|
|
/* current fps, once is programmed in hw */
|
|
int current_fps;
|
|
|
|
int panel_max_fps;
|
|
int panel_max_vtotal;
|
|
u32 mode_gpio_state;
|
|
u32 xstart_pix_align;
|
|
u32 width_pix_align;
|
|
u32 ystart_pix_align;
|
|
u32 height_pix_align;
|
|
u32 min_width;
|
|
u32 min_height;
|
|
u32 min_fps;
|
|
u32 max_fps;
|
|
u32 prg_fet;
|
|
|
|
u32 cont_splash_enabled;
|
|
bool esd_rdy;
|
|
bool partial_update_supported; /* value from dts if pu is supported */
|
|
bool partial_update_enabled; /* is pu currently allowed */
|
|
u32 dcs_cmd_by_left;
|
|
u32 partial_update_roi_merge;
|
|
struct ion_handle *splash_ihdl;
|
|
int panel_power_state;
|
|
int compression_mode;
|
|
|
|
uint32_t panel_dead;
|
|
u32 panel_force_dead;
|
|
u32 panel_orientation;
|
|
bool dynamic_switch_pending;
|
|
bool is_lpm_mode;
|
|
bool is_split_display; /* two DSIs in one display, pp split or not */
|
|
bool use_pingpong_split;
|
|
|
|
/*
|
|
* index[0] = left layer mixer, value of 0 not valid
|
|
* index[1] = right layer mixer, 0 is possible
|
|
*
|
|
* Ex(1): 1080x1920 display using single DSI and single lm, [1080 0]
|
|
* Ex(2): 1440x2560 display using two DSIs and two lms,
|
|
* each with 720x2560, [720 0]
|
|
* Ex(3): 1440x2560 display using single DSI w/ compression and
|
|
* single lm, [1440 0]
|
|
* Ex(4): 1440x2560 display using single DSI w/ compression and
|
|
* two lms, [720 720]
|
|
* Ex(5): 1080x1920 display using single DSI and two lm, [540 540]
|
|
* Ex(6): 1080x1920 display using single DSI and two lm,
|
|
* [880 400] - not practical but possible
|
|
*/
|
|
u32 lm_widths[2];
|
|
|
|
bool is_prim_panel;
|
|
bool is_pluggable;
|
|
char display_id[MDSS_DISPLAY_ID_MAX_LEN];
|
|
bool is_cec_supported;
|
|
|
|
/* refer sim_panel_modes enum for different modes */
|
|
u8 sim_panel_mode;
|
|
|
|
void *edid_data;
|
|
void *dba_data;
|
|
void *cec_data;
|
|
|
|
char panel_name[MDSS_MAX_PANEL_LEN];
|
|
struct mdss_mdp_pp_tear_check te;
|
|
|
|
/*
|
|
* Value of 2 only when single DSI is configured with 2 DSC
|
|
* encoders. When 2 encoders are used, currently both use
|
|
* same configuration.
|
|
*/
|
|
u8 dsc_enc_total; /* max 2 */
|
|
struct dsc_desc dsc;
|
|
|
|
struct lcd_panel_info lcdc;
|
|
struct fbc_panel_info fbc;
|
|
struct mipi_panel_info mipi;
|
|
struct lvds_panel_info lvds;
|
|
struct edp_panel_info edp;
|
|
|
|
bool is_dba_panel;
|
|
|
|
/*
|
|
* Delay(in ms) to accommodate s/w delay while
|
|
* configuring the event timer wakeup logic.
|
|
*/
|
|
u32 adjust_timer_delay_ms;
|
|
|
|
/* debugfs structure for the panel */
|
|
struct mdss_panel_debugfs_info *debugfs_info;
|
|
};
|
|
|
|
struct mdss_panel_timing {
|
|
struct list_head list;
|
|
const char *name;
|
|
|
|
u32 xres;
|
|
u32 yres;
|
|
|
|
u32 h_back_porch;
|
|
u32 h_front_porch;
|
|
u32 h_pulse_width;
|
|
u32 hsync_skew;
|
|
u32 v_back_porch;
|
|
u32 v_front_porch;
|
|
u32 v_pulse_width;
|
|
|
|
u32 border_top;
|
|
u32 border_bottom;
|
|
u32 border_left;
|
|
u32 border_right;
|
|
|
|
u32 lm_widths[2];
|
|
|
|
u64 clk_rate;
|
|
char frame_rate;
|
|
|
|
u8 dsc_enc_total;
|
|
struct dsc_desc dsc;
|
|
struct fbc_panel_info fbc;
|
|
u32 compression_mode;
|
|
|
|
struct mdss_mdp_pp_tear_check te;
|
|
};
|
|
|
|
struct mdss_panel_data {
|
|
struct mdss_panel_info panel_info;
|
|
void (*set_backlight) (struct mdss_panel_data *pdata, u32 bl_level);
|
|
unsigned char *mmss_cc_base;
|
|
|
|
/**
|
|
* event_handler() - callback handler for MDP core events
|
|
* @pdata: Pointer refering to the panel struct associated to this
|
|
* event. Can be used to retrieve panel info.
|
|
* @e: Event being generated, see enum mdss_intf_events
|
|
* @arg: Optional argument to pass some info from some events.
|
|
*
|
|
* Used to register handler to be used to propagate different events
|
|
* happening in MDP core driver. Panel driver can listen for any of
|
|
* these events to perform appropriate actions for panel initialization
|
|
* and teardown.
|
|
*/
|
|
int (*event_handler) (struct mdss_panel_data *pdata, int e, void *arg);
|
|
struct device_node *(*get_fb_node)(struct platform_device *pdev);
|
|
|
|
struct list_head timings_list;
|
|
struct mdss_panel_timing *current_timing;
|
|
bool active;
|
|
|
|
struct device_node *cfg_np; /* NULL if config node is not present */
|
|
struct mdss_panel_data *next;
|
|
};
|
|
|
|
struct mdss_panel_debugfs_info {
|
|
struct dentry *root;
|
|
struct mdss_panel_info panel_info;
|
|
u32 override_flag;
|
|
struct mdss_panel_debugfs_info *next;
|
|
};
|
|
|
|
/**
|
|
* mdss_get_panel_framerate() - get panel frame rate based on panel information
|
|
* @panel_info: Pointer to panel info containing all panel information
|
|
*/
|
|
static inline u32 mdss_panel_get_framerate(struct mdss_panel_info *panel_info)
|
|
{
|
|
u32 frame_rate, pixel_total;
|
|
u64 rate;
|
|
|
|
if (panel_info == NULL)
|
|
return DEFAULT_FRAME_RATE;
|
|
|
|
switch (panel_info->type) {
|
|
case MIPI_VIDEO_PANEL:
|
|
case MIPI_CMD_PANEL:
|
|
frame_rate = panel_info->mipi.frame_rate;
|
|
break;
|
|
case EDP_PANEL:
|
|
frame_rate = panel_info->edp.frame_rate;
|
|
break;
|
|
case WRITEBACK_PANEL:
|
|
frame_rate = DEFAULT_FRAME_RATE;
|
|
break;
|
|
default:
|
|
pixel_total = (panel_info->lcdc.h_back_porch +
|
|
panel_info->lcdc.h_front_porch +
|
|
panel_info->lcdc.h_pulse_width +
|
|
panel_info->xres) *
|
|
(panel_info->lcdc.v_back_porch +
|
|
panel_info->lcdc.v_front_porch +
|
|
panel_info->lcdc.v_pulse_width +
|
|
panel_info->yres);
|
|
if (pixel_total) {
|
|
rate = panel_info->clk_rate;
|
|
do_div(rate, pixel_total);
|
|
frame_rate = (u32)rate;
|
|
} else {
|
|
frame_rate = DEFAULT_FRAME_RATE;
|
|
}
|
|
break;
|
|
}
|
|
return frame_rate;
|
|
}
|
|
|
|
/*
|
|
* mdss_panel_get_vtotal() - return panel vertical height
|
|
* @pinfo: Pointer to panel info containing all panel information
|
|
*
|
|
* Returns the total height of the panel including any blanking regions
|
|
* which are not visible to user but used to calculate panel pixel clock.
|
|
*/
|
|
static inline int mdss_panel_get_vtotal(struct mdss_panel_info *pinfo)
|
|
{
|
|
return pinfo->yres + pinfo->lcdc.v_back_porch +
|
|
pinfo->lcdc.v_front_porch +
|
|
pinfo->lcdc.v_pulse_width+
|
|
pinfo->lcdc.border_top +
|
|
pinfo->lcdc.border_bottom;
|
|
}
|
|
|
|
/*
|
|
* mdss_panel_get_htotal() - return panel horizontal width
|
|
* @pinfo: Pointer to panel info containing all panel information
|
|
* @compression: true to factor fbc settings, false to ignore.
|
|
*
|
|
* Returns the total width of the panel including any blanking regions
|
|
* which are not visible to user but used for calculations. For certain
|
|
* usescases where the fbc parameters need to be ignored like bandwidth
|
|
* calculation, the appropriate flag can be passed.
|
|
*/
|
|
static inline int mdss_panel_get_htotal(struct mdss_panel_info *pinfo, bool
|
|
compression)
|
|
{
|
|
struct dsc_desc *dsc = NULL;
|
|
|
|
int adj_xres = pinfo->xres + pinfo->lcdc.border_left +
|
|
pinfo->lcdc.border_right;
|
|
|
|
if (compression) {
|
|
if (pinfo->compression_mode == COMPRESSION_DSC) {
|
|
dsc = &pinfo->dsc;
|
|
adj_xres = dsc->pclk_per_line;
|
|
} else if (pinfo->fbc.enabled) {
|
|
adj_xres = mult_frac(adj_xres,
|
|
pinfo->fbc.target_bpp, pinfo->bpp);
|
|
}
|
|
}
|
|
|
|
return adj_xres + pinfo->lcdc.h_back_porch +
|
|
pinfo->lcdc.h_front_porch +
|
|
pinfo->lcdc.h_pulse_width;
|
|
}
|
|
|
|
static inline bool is_dsc_compression(struct mdss_panel_info *pinfo)
|
|
{
|
|
if (pinfo)
|
|
return (pinfo->compression_mode == COMPRESSION_DSC);
|
|
|
|
return false;
|
|
}
|
|
|
|
int mdss_register_panel(struct platform_device *pdev,
|
|
struct mdss_panel_data *pdata);
|
|
|
|
/*
|
|
* mdss_panel_is_power_off: - checks if a panel is off
|
|
* @panel_power_state: enum identifying the power state to be checked
|
|
*/
|
|
static inline bool mdss_panel_is_power_off(int panel_power_state)
|
|
{
|
|
return (panel_power_state == MDSS_PANEL_POWER_OFF);
|
|
}
|
|
|
|
/**
|
|
* mdss_panel_is_power_on_interactive: - checks if a panel is on and interactive
|
|
* @panel_power_state: enum identifying the power state to be checked
|
|
*
|
|
* This function returns true only is the panel is fully interactive and
|
|
* opertaing in normal mode.
|
|
*/
|
|
static inline bool mdss_panel_is_power_on_interactive(int panel_power_state)
|
|
{
|
|
return (panel_power_state == MDSS_PANEL_POWER_ON);
|
|
}
|
|
|
|
/**
|
|
* mdss_panel_is_panel_power_on: - checks if a panel is on
|
|
* @panel_power_state: enum identifying the power state to be checked
|
|
*
|
|
* A panel is considered to be on as long as it can accept any commands
|
|
* or data. Sometimes it is posible to program the panel to be in a low
|
|
* power non-interactive state. This function returns false only if panel
|
|
* has explicitly been turned off.
|
|
*/
|
|
static inline bool mdss_panel_is_power_on(int panel_power_state)
|
|
{
|
|
return !mdss_panel_is_power_off(panel_power_state);
|
|
}
|
|
|
|
/**
|
|
* mdss_panel_is_panel_power_on_lp: - checks if a panel is in a low power mode
|
|
* @pdata: pointer to the panel struct associated to the panel
|
|
* @panel_power_state: enum identifying the power state to be checked
|
|
*
|
|
* This function returns true if the panel is in an intermediate low power
|
|
* state where it is still on but not fully interactive. It may or may not
|
|
* accept any commands and display updates.
|
|
*/
|
|
static inline bool mdss_panel_is_power_on_lp(int panel_power_state)
|
|
{
|
|
return !mdss_panel_is_power_off(panel_power_state) &&
|
|
!mdss_panel_is_power_on_interactive(panel_power_state);
|
|
}
|
|
|
|
/**
|
|
* mdss_panel_is_panel_power_on_ulp: - checks if panel is in ultra low power mode
|
|
* @pdata: pointer to the panel struct associated to the panel
|
|
* @panel_power_state: enum identifying the power state to be checked
|
|
*
|
|
* This function returns true if the panel is in a ultra low power
|
|
* state where it is still on but cannot recieve any display updates.
|
|
*/
|
|
static inline bool mdss_panel_is_power_on_ulp(int panel_power_state)
|
|
{
|
|
return panel_power_state == MDSS_PANEL_POWER_LP2;
|
|
}
|
|
|
|
/**
|
|
* mdss_panel_calc_frame_rate() - calculate panel frame rate based on panel timing
|
|
* information.
|
|
* @panel_info: Pointer to panel info containing all panel information
|
|
*/
|
|
static inline u8 mdss_panel_calc_frame_rate(struct mdss_panel_info *pinfo)
|
|
{
|
|
u32 pixel_total = 0;
|
|
u8 frame_rate = 0;
|
|
unsigned long pclk_rate = pinfo->clk_rate;
|
|
|
|
pixel_total = (pinfo->lcdc.h_back_porch +
|
|
pinfo->lcdc.h_front_porch +
|
|
pinfo->lcdc.h_pulse_width +
|
|
pinfo->xres) *
|
|
(pinfo->lcdc.v_back_porch +
|
|
pinfo->lcdc.v_front_porch +
|
|
pinfo->lcdc.v_pulse_width +
|
|
pinfo->yres);
|
|
|
|
if (pclk_rate && pixel_total)
|
|
frame_rate =
|
|
DIV_ROUND_CLOSEST(pclk_rate, pixel_total);
|
|
else
|
|
frame_rate = DEFAULT_FRAME_RATE;
|
|
|
|
return frame_rate;
|
|
}
|
|
|
|
/**
|
|
* mdss_panel_intf_type: - checks if a given intf type is primary
|
|
* @intf_val: panel interface type of the individual controller
|
|
*
|
|
* Individual controller queries with MDP to check if it is
|
|
* configured as the primary interface.
|
|
*
|
|
* returns a pointer to the configured structure mdss_panel_cfg
|
|
* to the controller that's configured as the primary panel interface.
|
|
* returns NULL on error or if @intf_val is not the configured
|
|
* controller.
|
|
*/
|
|
struct mdss_panel_cfg *mdss_panel_intf_type(int intf_val);
|
|
|
|
/**
|
|
* mdss_is_ready() - checks if mdss is probed and ready
|
|
*
|
|
* Checks if mdss resources have been initialized
|
|
*
|
|
* returns true if mdss is ready, else returns false.
|
|
*/
|
|
bool mdss_is_ready(void);
|
|
int mdss_rect_cmp(struct mdss_rect *rect1, struct mdss_rect *rect2);
|
|
|
|
/**
|
|
* mdss_panel_override_te_params() - overrides TE params to enable SW TE
|
|
* @pinfo: panel info
|
|
*/
|
|
void mdss_panel_override_te_params(struct mdss_panel_info *pinfo);
|
|
|
|
/**
|
|
* mdss_panel_dsc_parameters_calc: calculate DSC parameters
|
|
* @dsc: pointer to DSC structure associated with panel_info
|
|
*/
|
|
void mdss_panel_dsc_parameters_calc(struct dsc_desc *dsc);
|
|
|
|
/**
|
|
* mdss_panel_dsc_update_pic_dim: update DSC structure with picture dimension
|
|
* @dsc: pointer to DSC structure associated with panel_info
|
|
* @pic_width: Picture width
|
|
* @pic_height: Picture height
|
|
*/
|
|
void mdss_panel_dsc_update_pic_dim(struct dsc_desc *dsc,
|
|
int pic_width, int pic_height);
|
|
|
|
/**
|
|
* mdss_panel_dsc_initial_line_calc: update DSC initial line buffering
|
|
* @dsc: pointer to DSC structure associated with panel_info
|
|
* @enc_ip_width: uncompressed input width for DSC enc represented by @dsc
|
|
* i.e.
|
|
* * 720 for full frame single_display_dual_lm: 1440x2560
|
|
* * 1080 for full frame dual_display_dual_lm: 2160x3840
|
|
* * 360 for partial frame single_display_dual_lm: 360x2560
|
|
*/
|
|
void mdss_panel_dsc_initial_line_calc(struct dsc_desc *dsc, int enc_ip_width);
|
|
|
|
/**
|
|
* mdss_panel_dsc_pclk_param_calc: calculate DSC params related to DSI
|
|
* @dsc: pointer to DSC structure associated with panel_info
|
|
* @intf_width: Uncompressed width per interface
|
|
* i.e.
|
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* * 1440 for full frame single_display_dual_lm: 1440x2560
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* * 1080 for full frame dual_display_dual_lm: 2160x3840
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* * 720 for partial frame single_display_dual_lm: 720x2560
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*/
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void mdss_panel_dsc_pclk_param_calc(struct dsc_desc *dsc, int intf_width);
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|
|
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/**
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* mdss_panel_dsc_prepare_pps_buf - prepares Picture Parameter Set to be sent to panel
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* @dsc: pointer to DSC structure associated with panel_info
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* @buf: buffer that holds PPS
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* @pps_id: pps_identifier
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* @major: major version of the DSC encoder
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|
* @minot: minor version of the DSC encoder
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|
*
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|
* returns length of the PPS buffer.
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|
*/
|
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int mdss_panel_dsc_prepare_pps_buf(struct dsc_desc *dsc, char *buf,
|
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int pps_id, int major, int minor);
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|
#ifdef CONFIG_FB_MSM_MDSS
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|
int mdss_panel_debugfs_init(struct mdss_panel_info *panel_info,
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|
char const *panel_name);
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|
void mdss_panel_debugfs_cleanup(struct mdss_panel_info *panel_info);
|
|
void mdss_panel_debugfsinfo_to_panelinfo(struct mdss_panel_info *panel_info);
|
|
|
|
/*
|
|
* mdss_panel_info_from_timing() - populate panel info from panel timing
|
|
* @pt: pointer to source panel timing
|
|
* @pinfo: pointer to destination panel info
|
|
*
|
|
* Populates relevant data from panel timing into panel info
|
|
*/
|
|
void mdss_panel_info_from_timing(struct mdss_panel_timing *pt,
|
|
struct mdss_panel_info *pinfo);
|
|
|
|
/**
|
|
* mdss_panel_get_timing_by_name() - return panel timing with matching name
|
|
* @pdata: pointer to panel data struct containing list of panel timings
|
|
* @name: name of the panel timing to be returned
|
|
*
|
|
* Looks through list of timings provided in panel data and returns pointer
|
|
* to panel timing matching it. If none is found, NULL is returned.
|
|
*/
|
|
struct mdss_panel_timing *mdss_panel_get_timing_by_name(
|
|
struct mdss_panel_data *pdata,
|
|
const char *name);
|
|
#else
|
|
static inline int mdss_panel_debugfs_init(
|
|
struct mdss_panel_info *panel_info,
|
|
char const *panel_name) { return 0; };
|
|
static inline void mdss_panel_debugfs_cleanup(
|
|
struct mdss_panel_info *panel_info) { };
|
|
static inline void mdss_panel_debugfsinfo_to_panelinfo(
|
|
struct mdss_panel_info *panel_info) { };
|
|
static inline void mdss_panel_info_from_timing(struct mdss_panel_timing *pt,
|
|
struct mdss_panel_info *pinfo) { };
|
|
static inline struct mdss_panel_timing *mdss_panel_get_timing_by_name(
|
|
struct mdss_panel_data *pdata,
|
|
const char *name) { return NULL; };
|
|
#endif
|
|
#endif /* MDSS_PANEL_H */
|