2686 lines
70 KiB
Plaintext
2686 lines
70 KiB
Plaintext
/*
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* DO NOT EDIT - This file is automatically generated
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* from the following source files:
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*
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* $Id: //depot/aic7xxx/aic7xxx/aic79xx.seq#120 $
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* $Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#77 $
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*/
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typedef int (ahd_reg_print_t)(u_int, u_int *, u_int);
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typedef struct ahd_reg_parse_entry {
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char *name;
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uint8_t value;
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uint8_t mask;
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} ahd_reg_parse_entry_t;
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_mode_ptr_print;
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#else
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#define ahd_mode_ptr_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "MODE_PTR", 0x00, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_intstat_print;
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#else
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#define ahd_intstat_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "INTSTAT", 0x01, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_seqintcode_print;
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#else
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#define ahd_seqintcode_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "SEQINTCODE", 0x02, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_error_print;
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#else
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#define ahd_error_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "ERROR", 0x04, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_hescb_qoff_print;
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#else
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#define ahd_hescb_qoff_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "HESCB_QOFF", 0x08, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_hs_mailbox_print;
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#else
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#define ahd_hs_mailbox_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "HS_MAILBOX", 0x0b, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_seqintstat_print;
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#else
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#define ahd_seqintstat_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "SEQINTSTAT", 0x0c, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_clrseqintstat_print;
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#else
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#define ahd_clrseqintstat_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "CLRSEQINTSTAT", 0x0c, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_swtimer_print;
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#else
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#define ahd_swtimer_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "SWTIMER", 0x0e, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_sescb_qoff_print;
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#else
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#define ahd_sescb_qoff_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "SESCB_QOFF", 0x12, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_intctl_print;
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#else
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#define ahd_intctl_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "INTCTL", 0x18, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_dfcntrl_print;
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#else
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#define ahd_dfcntrl_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "DFCNTRL", 0x19, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_dfstatus_print;
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#else
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#define ahd_dfstatus_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "DFSTATUS", 0x1a, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_sg_cache_shadow_print;
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#else
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#define ahd_sg_cache_shadow_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "SG_CACHE_SHADOW", 0x1b, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_lqin_print;
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#else
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#define ahd_lqin_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "LQIN", 0x20, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_lunptr_print;
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#else
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#define ahd_lunptr_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "LUNPTR", 0x22, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_cmdlenptr_print;
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#else
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#define ahd_cmdlenptr_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "CMDLENPTR", 0x25, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_attrptr_print;
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#else
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#define ahd_attrptr_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "ATTRPTR", 0x26, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_flagptr_print;
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#else
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#define ahd_flagptr_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "FLAGPTR", 0x27, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_cmdptr_print;
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#else
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#define ahd_cmdptr_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "CMDPTR", 0x28, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_qnextptr_print;
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#else
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#define ahd_qnextptr_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "QNEXTPTR", 0x29, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_abrtbyteptr_print;
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#else
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#define ahd_abrtbyteptr_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "ABRTBYTEPTR", 0x2b, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_abrtbitptr_print;
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#else
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#define ahd_abrtbitptr_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "ABRTBITPTR", 0x2c, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_lunlen_print;
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#else
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#define ahd_lunlen_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "LUNLEN", 0x30, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_cdblimit_print;
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#else
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#define ahd_cdblimit_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "CDBLIMIT", 0x31, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_maxcmd_print;
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#else
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#define ahd_maxcmd_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "MAXCMD", 0x32, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_maxcmdcnt_print;
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#else
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#define ahd_maxcmdcnt_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "MAXCMDCNT", 0x33, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_lqctl1_print;
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#else
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#define ahd_lqctl1_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "LQCTL1", 0x38, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_lqctl2_print;
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#else
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#define ahd_lqctl2_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "LQCTL2", 0x39, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_scsiseq0_print;
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#else
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#define ahd_scsiseq0_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "SCSISEQ0", 0x3a, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_scsiseq1_print;
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#else
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#define ahd_scsiseq1_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "SCSISEQ1", 0x3b, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_sxfrctl0_print;
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#else
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#define ahd_sxfrctl0_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "SXFRCTL0", 0x3c, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_dffstat_print;
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#else
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#define ahd_dffstat_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "DFFSTAT", 0x3f, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_multargid_print;
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#else
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#define ahd_multargid_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "MULTARGID", 0x40, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_scsisigi_print;
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#else
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#define ahd_scsisigi_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "SCSISIGI", 0x41, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_scsiphase_print;
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#else
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#define ahd_scsiphase_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "SCSIPHASE", 0x42, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_scsidat_print;
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#else
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#define ahd_scsidat_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "SCSIDAT", 0x44, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_scsibus_print;
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#else
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#define ahd_scsibus_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "SCSIBUS", 0x46, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_targidin_print;
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#else
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#define ahd_targidin_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "TARGIDIN", 0x48, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_selid_print;
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#else
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#define ahd_selid_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "SELID", 0x49, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_sblkctl_print;
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#else
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#define ahd_sblkctl_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "SBLKCTL", 0x4a, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_sstat0_print;
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#else
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#define ahd_sstat0_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "SSTAT0", 0x4b, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_simode0_print;
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#else
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#define ahd_simode0_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "SIMODE0", 0x4b, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_sstat1_print;
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#else
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#define ahd_sstat1_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "SSTAT1", 0x4c, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_sstat2_print;
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#else
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#define ahd_sstat2_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "SSTAT2", 0x4d, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_clrsint2_print;
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#else
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#define ahd_clrsint2_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "CLRSINT2", 0x4d, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_perrdiag_print;
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#else
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#define ahd_perrdiag_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "PERRDIAG", 0x4e, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_lqistate_print;
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#else
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#define ahd_lqistate_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "LQISTATE", 0x4e, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_soffcnt_print;
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#else
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#define ahd_soffcnt_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "SOFFCNT", 0x4f, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_lqostate_print;
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#else
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#define ahd_lqostate_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "LQOSTATE", 0x4f, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_lqistat0_print;
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#else
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#define ahd_lqistat0_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "LQISTAT0", 0x50, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_clrlqiint0_print;
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#else
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#define ahd_clrlqiint0_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "CLRLQIINT0", 0x50, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_lqimode0_print;
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#else
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#define ahd_lqimode0_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "LQIMODE0", 0x50, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_lqimode1_print;
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#else
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#define ahd_lqimode1_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "LQIMODE1", 0x51, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_lqistat1_print;
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#else
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#define ahd_lqistat1_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "LQISTAT1", 0x51, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_clrlqiint1_print;
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#else
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#define ahd_clrlqiint1_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "CLRLQIINT1", 0x51, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_lqistat2_print;
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#else
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#define ahd_lqistat2_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "LQISTAT2", 0x52, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahd_reg_print_t ahd_sstat3_print;
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#else
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#define ahd_sstat3_print(regvalue, cur_col, wrap) \
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ahd_print_register(NULL, 0, "SSTAT3", 0x53, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_simode3_print;
|
|
#else
|
|
#define ahd_simode3_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "SIMODE3", 0x53, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_clrsint3_print;
|
|
#else
|
|
#define ahd_clrsint3_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "CLRSINT3", 0x53, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_lqostat0_print;
|
|
#else
|
|
#define ahd_lqostat0_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "LQOSTAT0", 0x54, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_clrlqoint0_print;
|
|
#else
|
|
#define ahd_clrlqoint0_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "CLRLQOINT0", 0x54, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_lqomode0_print;
|
|
#else
|
|
#define ahd_lqomode0_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "LQOMODE0", 0x54, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_lqomode1_print;
|
|
#else
|
|
#define ahd_lqomode1_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "LQOMODE1", 0x55, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_lqostat1_print;
|
|
#else
|
|
#define ahd_lqostat1_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "LQOSTAT1", 0x55, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_clrlqoint1_print;
|
|
#else
|
|
#define ahd_clrlqoint1_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "CLRLQOINT1", 0x55, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_lqostat2_print;
|
|
#else
|
|
#define ahd_lqostat2_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "LQOSTAT2", 0x56, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_os_space_cnt_print;
|
|
#else
|
|
#define ahd_os_space_cnt_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "OS_SPACE_CNT", 0x56, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_simode1_print;
|
|
#else
|
|
#define ahd_simode1_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "SIMODE1", 0x57, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_gsfifo_print;
|
|
#else
|
|
#define ahd_gsfifo_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "GSFIFO", 0x58, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_dffsxfrctl_print;
|
|
#else
|
|
#define ahd_dffsxfrctl_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "DFFSXFRCTL", 0x5a, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_lqoscsctl_print;
|
|
#else
|
|
#define ahd_lqoscsctl_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "LQOSCSCTL", 0x5a, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_nextscb_print;
|
|
#else
|
|
#define ahd_nextscb_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "NEXTSCB", 0x5a, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_clrseqintsrc_print;
|
|
#else
|
|
#define ahd_clrseqintsrc_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "CLRSEQINTSRC", 0x5b, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_seqintsrc_print;
|
|
#else
|
|
#define ahd_seqintsrc_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "SEQINTSRC", 0x5b, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_currscb_print;
|
|
#else
|
|
#define ahd_currscb_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "CURRSCB", 0x5c, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_seqimode_print;
|
|
#else
|
|
#define ahd_seqimode_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "SEQIMODE", 0x5c, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_mdffstat_print;
|
|
#else
|
|
#define ahd_mdffstat_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "MDFFSTAT", 0x5d, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_lastscb_print;
|
|
#else
|
|
#define ahd_lastscb_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "LASTSCB", 0x5e, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_negoaddr_print;
|
|
#else
|
|
#define ahd_negoaddr_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "NEGOADDR", 0x60, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_negperiod_print;
|
|
#else
|
|
#define ahd_negperiod_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "NEGPERIOD", 0x61, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_negoffset_print;
|
|
#else
|
|
#define ahd_negoffset_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "NEGOFFSET", 0x62, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_negppropts_print;
|
|
#else
|
|
#define ahd_negppropts_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "NEGPPROPTS", 0x63, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_negconopts_print;
|
|
#else
|
|
#define ahd_negconopts_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "NEGCONOPTS", 0x64, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_annexcol_print;
|
|
#else
|
|
#define ahd_annexcol_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "ANNEXCOL", 0x65, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_annexdat_print;
|
|
#else
|
|
#define ahd_annexdat_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "ANNEXDAT", 0x66, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_scschkn_print;
|
|
#else
|
|
#define ahd_scschkn_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "SCSCHKN", 0x66, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_iownid_print;
|
|
#else
|
|
#define ahd_iownid_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "IOWNID", 0x67, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_shcnt_print;
|
|
#else
|
|
#define ahd_shcnt_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "SHCNT", 0x68, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_townid_print;
|
|
#else
|
|
#define ahd_townid_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "TOWNID", 0x69, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_seloid_print;
|
|
#else
|
|
#define ahd_seloid_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "SELOID", 0x6b, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_scbhaddr_print;
|
|
#else
|
|
#define ahd_scbhaddr_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "SCBHADDR", 0x7c, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_sghaddr_print;
|
|
#else
|
|
#define ahd_sghaddr_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "SGHADDR", 0x7c, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_scbhcnt_print;
|
|
#else
|
|
#define ahd_scbhcnt_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "SCBHCNT", 0x84, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_sghcnt_print;
|
|
#else
|
|
#define ahd_sghcnt_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "SGHCNT", 0x84, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_pcixctl_print;
|
|
#else
|
|
#define ahd_pcixctl_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "PCIXCTL", 0x93, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_dchspltstat0_print;
|
|
#else
|
|
#define ahd_dchspltstat0_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "DCHSPLTSTAT0", 0x96, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_dchspltstat1_print;
|
|
#else
|
|
#define ahd_dchspltstat1_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "DCHSPLTSTAT1", 0x97, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_sgspltstat0_print;
|
|
#else
|
|
#define ahd_sgspltstat0_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "SGSPLTSTAT0", 0x9e, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_sgspltstat1_print;
|
|
#else
|
|
#define ahd_sgspltstat1_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "SGSPLTSTAT1", 0x9f, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_df0pcistat_print;
|
|
#else
|
|
#define ahd_df0pcistat_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "DF0PCISTAT", 0xa0, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_reg0_print;
|
|
#else
|
|
#define ahd_reg0_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "REG0", 0xa0, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_reg_isr_print;
|
|
#else
|
|
#define ahd_reg_isr_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "REG_ISR", 0xa4, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_sg_state_print;
|
|
#else
|
|
#define ahd_sg_state_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "SG_STATE", 0xa6, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_targpcistat_print;
|
|
#else
|
|
#define ahd_targpcistat_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "TARGPCISTAT", 0xa7, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_scbautoptr_print;
|
|
#else
|
|
#define ahd_scbautoptr_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "SCBAUTOPTR", 0xab, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_ccscbaddr_print;
|
|
#else
|
|
#define ahd_ccscbaddr_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "CCSCBADDR", 0xac, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_ccscbctl_print;
|
|
#else
|
|
#define ahd_ccscbctl_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "CCSCBCTL", 0xad, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_ccsgctl_print;
|
|
#else
|
|
#define ahd_ccsgctl_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "CCSGCTL", 0xad, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_ccscbram_print;
|
|
#else
|
|
#define ahd_ccscbram_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "CCSCBRAM", 0xb0, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_brddat_print;
|
|
#else
|
|
#define ahd_brddat_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "BRDDAT", 0xb8, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_seeadr_print;
|
|
#else
|
|
#define ahd_seeadr_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "SEEADR", 0xba, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_seedat_print;
|
|
#else
|
|
#define ahd_seedat_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "SEEDAT", 0xbc, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_seectl_print;
|
|
#else
|
|
#define ahd_seectl_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "SEECTL", 0xbe, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_seestat_print;
|
|
#else
|
|
#define ahd_seestat_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "SEESTAT", 0xbe, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_dspdatactl_print;
|
|
#else
|
|
#define ahd_dspdatactl_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "DSPDATACTL", 0xc1, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_dspselect_print;
|
|
#else
|
|
#define ahd_dspselect_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "DSPSELECT", 0xc4, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_wrtbiasctl_print;
|
|
#else
|
|
#define ahd_wrtbiasctl_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "WRTBIASCTL", 0xc5, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_seqctl0_print;
|
|
#else
|
|
#define ahd_seqctl0_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "SEQCTL0", 0xd6, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_seqintctl_print;
|
|
#else
|
|
#define ahd_seqintctl_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "SEQINTCTL", 0xd9, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_prgmcnt_print;
|
|
#else
|
|
#define ahd_prgmcnt_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "PRGMCNT", 0xde, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_none_print;
|
|
#else
|
|
#define ahd_none_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "NONE", 0xea, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_intvec1_addr_print;
|
|
#else
|
|
#define ahd_intvec1_addr_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "INTVEC1_ADDR", 0xf4, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_curaddr_print;
|
|
#else
|
|
#define ahd_curaddr_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "CURADDR", 0xf4, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_intvec2_addr_print;
|
|
#else
|
|
#define ahd_intvec2_addr_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "INTVEC2_ADDR", 0xf6, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_longjmp_addr_print;
|
|
#else
|
|
#define ahd_longjmp_addr_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "LONGJMP_ADDR", 0xf8, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_accum_save_print;
|
|
#else
|
|
#define ahd_accum_save_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "ACCUM_SAVE", 0xfa, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_waiting_scb_tails_print;
|
|
#else
|
|
#define ahd_waiting_scb_tails_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "WAITING_SCB_TAILS", 0x100, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_sram_base_print;
|
|
#else
|
|
#define ahd_sram_base_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "SRAM_BASE", 0x100, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_waiting_tid_head_print;
|
|
#else
|
|
#define ahd_waiting_tid_head_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "WAITING_TID_HEAD", 0x120, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_waiting_tid_tail_print;
|
|
#else
|
|
#define ahd_waiting_tid_tail_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "WAITING_TID_TAIL", 0x122, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_next_queued_scb_addr_print;
|
|
#else
|
|
#define ahd_next_queued_scb_addr_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "NEXT_QUEUED_SCB_ADDR", 0x124, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_complete_scb_head_print;
|
|
#else
|
|
#define ahd_complete_scb_head_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "COMPLETE_SCB_HEAD", 0x128, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_complete_scb_dmainprog_head_print;
|
|
#else
|
|
#define ahd_complete_scb_dmainprog_head_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "COMPLETE_SCB_DMAINPROG_HEAD", 0x12a, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_complete_dma_scb_head_print;
|
|
#else
|
|
#define ahd_complete_dma_scb_head_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "COMPLETE_DMA_SCB_HEAD", 0x12c, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_complete_dma_scb_tail_print;
|
|
#else
|
|
#define ahd_complete_dma_scb_tail_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "COMPLETE_DMA_SCB_TAIL", 0x12e, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_complete_on_qfreeze_head_print;
|
|
#else
|
|
#define ahd_complete_on_qfreeze_head_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "COMPLETE_ON_QFREEZE_HEAD", 0x130, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_qfreeze_count_print;
|
|
#else
|
|
#define ahd_qfreeze_count_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "QFREEZE_COUNT", 0x132, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_kernel_qfreeze_count_print;
|
|
#else
|
|
#define ahd_kernel_qfreeze_count_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "KERNEL_QFREEZE_COUNT", 0x134, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_saved_mode_print;
|
|
#else
|
|
#define ahd_saved_mode_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "SAVED_MODE", 0x136, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_msg_out_print;
|
|
#else
|
|
#define ahd_msg_out_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "MSG_OUT", 0x137, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_seq_flags_print;
|
|
#else
|
|
#define ahd_seq_flags_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "SEQ_FLAGS", 0x139, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_lastphase_print;
|
|
#else
|
|
#define ahd_lastphase_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "LASTPHASE", 0x13c, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_qoutfifo_entry_valid_tag_print;
|
|
#else
|
|
#define ahd_qoutfifo_entry_valid_tag_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "QOUTFIFO_ENTRY_VALID_TAG", 0x13d, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_kernel_tqinpos_print;
|
|
#else
|
|
#define ahd_kernel_tqinpos_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "KERNEL_TQINPOS", 0x13e, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_qoutfifo_next_addr_print;
|
|
#else
|
|
#define ahd_qoutfifo_next_addr_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "QOUTFIFO_NEXT_ADDR", 0x144, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_last_msg_print;
|
|
#else
|
|
#define ahd_last_msg_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "LAST_MSG", 0x14a, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_scsiseq_template_print;
|
|
#else
|
|
#define ahd_scsiseq_template_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "SCSISEQ_TEMPLATE", 0x14b, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_initiator_tag_print;
|
|
#else
|
|
#define ahd_initiator_tag_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "INITIATOR_TAG", 0x14c, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_seq_flags2_print;
|
|
#else
|
|
#define ahd_seq_flags2_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "SEQ_FLAGS2", 0x14d, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_allocfifo_scbptr_print;
|
|
#else
|
|
#define ahd_allocfifo_scbptr_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "ALLOCFIFO_SCBPTR", 0x14e, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_int_coalescing_timer_print;
|
|
#else
|
|
#define ahd_int_coalescing_timer_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "INT_COALESCING_TIMER", 0x150, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_int_coalescing_maxcmds_print;
|
|
#else
|
|
#define ahd_int_coalescing_maxcmds_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "INT_COALESCING_MAXCMDS", 0x152, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_int_coalescing_mincmds_print;
|
|
#else
|
|
#define ahd_int_coalescing_mincmds_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "INT_COALESCING_MINCMDS", 0x153, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_cmds_pending_print;
|
|
#else
|
|
#define ahd_cmds_pending_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "CMDS_PENDING", 0x154, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_int_coalescing_cmdcount_print;
|
|
#else
|
|
#define ahd_int_coalescing_cmdcount_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "INT_COALESCING_CMDCOUNT", 0x156, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_local_hs_mailbox_print;
|
|
#else
|
|
#define ahd_local_hs_mailbox_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "LOCAL_HS_MAILBOX", 0x157, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_cmdsize_table_print;
|
|
#else
|
|
#define ahd_cmdsize_table_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "CMDSIZE_TABLE", 0x158, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_mk_message_scb_print;
|
|
#else
|
|
#define ahd_mk_message_scb_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "MK_MESSAGE_SCB", 0x160, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_mk_message_scsiid_print;
|
|
#else
|
|
#define ahd_mk_message_scsiid_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "MK_MESSAGE_SCSIID", 0x162, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_scb_base_print;
|
|
#else
|
|
#define ahd_scb_base_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "SCB_BASE", 0x180, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_scb_residual_datacnt_print;
|
|
#else
|
|
#define ahd_scb_residual_datacnt_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "SCB_RESIDUAL_DATACNT", 0x180, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_scb_sense_busaddr_print;
|
|
#else
|
|
#define ahd_scb_sense_busaddr_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "SCB_SENSE_BUSADDR", 0x18c, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_scb_tag_print;
|
|
#else
|
|
#define ahd_scb_tag_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "SCB_TAG", 0x190, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_scb_control_print;
|
|
#else
|
|
#define ahd_scb_control_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "SCB_CONTROL", 0x192, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_scb_scsiid_print;
|
|
#else
|
|
#define ahd_scb_scsiid_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "SCB_SCSIID", 0x193, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_scb_lun_print;
|
|
#else
|
|
#define ahd_scb_lun_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "SCB_LUN", 0x194, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_scb_task_attribute_print;
|
|
#else
|
|
#define ahd_scb_task_attribute_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "SCB_TASK_ATTRIBUTE", 0x195, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_scb_task_management_print;
|
|
#else
|
|
#define ahd_scb_task_management_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "SCB_TASK_MANAGEMENT", 0x197, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_scb_dataptr_print;
|
|
#else
|
|
#define ahd_scb_dataptr_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "SCB_DATAPTR", 0x198, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_scb_datacnt_print;
|
|
#else
|
|
#define ahd_scb_datacnt_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "SCB_DATACNT", 0x1a0, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_scb_sgptr_print;
|
|
#else
|
|
#define ahd_scb_sgptr_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "SCB_SGPTR", 0x1a4, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_scb_busaddr_print;
|
|
#else
|
|
#define ahd_scb_busaddr_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "SCB_BUSADDR", 0x1a8, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_scb_next2_print;
|
|
#else
|
|
#define ahd_scb_next2_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "SCB_NEXT2", 0x1ae, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
#if AIC_DEBUG_REGISTERS
|
|
ahd_reg_print_t ahd_scb_disconnected_lists_print;
|
|
#else
|
|
#define ahd_scb_disconnected_lists_print(regvalue, cur_col, wrap) \
|
|
ahd_print_register(NULL, 0, "SCB_DISCONNECTED_LISTS", 0x1b8, regvalue, cur_col, wrap)
|
|
#endif
|
|
|
|
|
|
#define MODE_PTR 0x00
|
|
#define DST_MODE 0x70
|
|
#define SRC_MODE 0x07
|
|
|
|
#define INTSTAT 0x01
|
|
#define INT_PEND 0xff
|
|
#define HWERRINT 0x80
|
|
#define BRKADRINT 0x40
|
|
#define SWTMINT 0x20
|
|
#define PCIINT 0x10
|
|
#define SCSIINT 0x08
|
|
#define SEQINT 0x04
|
|
#define CMDCMPLT 0x02
|
|
#define SPLTINT 0x01
|
|
|
|
#define SEQINTCODE 0x02
|
|
#define BAD_SCB_STATUS 0x1a
|
|
#define SAW_HWERR 0x19
|
|
#define TRACEPOINT3 0x18
|
|
#define TRACEPOINT2 0x17
|
|
#define TRACEPOINT1 0x16
|
|
#define TRACEPOINT0 0x15
|
|
#define TASKMGMT_CMD_CMPLT_OKAY 0x14
|
|
#define TASKMGMT_FUNC_COMPLETE 0x13
|
|
#define ENTERING_NONPACK 0x12
|
|
#define CFG4OVERRUN 0x11
|
|
#define STATUS_OVERRUN 0x10
|
|
#define CFG4ISTAT_INTR 0x0f
|
|
#define INVALID_SEQINT 0x0e
|
|
#define ILLEGAL_PHASE 0x0d
|
|
#define DUMP_CARD_STATE 0x0c
|
|
#define MISSED_BUSFREE 0x0b
|
|
#define MKMSG_FAILED 0x0a
|
|
#define DATA_OVERRUN 0x09
|
|
#define BAD_STATUS 0x08
|
|
#define HOST_MSG_LOOP 0x07
|
|
#define PDATA_REINIT 0x06
|
|
#define IGN_WIDE_RES 0x05
|
|
#define NO_MATCH 0x04
|
|
#define PROTO_VIOLATION 0x03
|
|
#define SEND_REJECT 0x02
|
|
#define BAD_PHASE 0x01
|
|
#define NO_SEQINT 0x00
|
|
|
|
#define CLRINT 0x03
|
|
#define CLRHWERRINT 0x80
|
|
#define CLRBRKADRINT 0x40
|
|
#define CLRSWTMINT 0x20
|
|
#define CLRPCIINT 0x10
|
|
#define CLRSCSIINT 0x08
|
|
#define CLRSEQINT 0x04
|
|
#define CLRCMDINT 0x02
|
|
#define CLRSPLTINT 0x01
|
|
|
|
#define ERROR 0x04
|
|
#define CIOPARERR 0x80
|
|
#define CIOACCESFAIL 0x40
|
|
#define MPARERR 0x20
|
|
#define DPARERR 0x10
|
|
#define SQPARERR 0x08
|
|
#define ILLOPCODE 0x04
|
|
#define DSCTMOUT 0x02
|
|
|
|
#define CLRERR 0x04
|
|
#define CLRCIOPARERR 0x80
|
|
#define CLRCIOACCESFAIL 0x40
|
|
#define CLRMPARERR 0x20
|
|
#define CLRDPARERR 0x10
|
|
#define CLRSQPARERR 0x08
|
|
#define CLRILLOPCODE 0x04
|
|
#define CLRDSCTMOUT 0x02
|
|
|
|
#define HCNTRL 0x05
|
|
#define SEQ_RESET 0x80
|
|
#define POWRDN 0x40
|
|
#define SWINT 0x10
|
|
#define SWTIMER_START_B 0x08
|
|
#define PAUSE 0x04
|
|
#define INTEN 0x02
|
|
#define CHIPRST 0x01
|
|
#define CHIPRSTACK 0x01
|
|
|
|
#define HNSCB_QOFF 0x06
|
|
|
|
#define HESCB_QOFF 0x08
|
|
|
|
#define HS_MAILBOX 0x0b
|
|
#define HOST_TQINPOS 0x80
|
|
#define ENINT_COALESCE 0x40
|
|
|
|
#define SEQINTSTAT 0x0c
|
|
#define SEQ_SWTMRTO 0x10
|
|
#define SEQ_SEQINT 0x08
|
|
#define SEQ_SCSIINT 0x04
|
|
#define SEQ_PCIINT 0x02
|
|
#define SEQ_SPLTINT 0x01
|
|
|
|
#define CLRSEQINTSTAT 0x0c
|
|
#define CLRSEQ_SWTMRTO 0x10
|
|
#define CLRSEQ_SEQINT 0x08
|
|
#define CLRSEQ_SCSIINT 0x04
|
|
#define CLRSEQ_PCIINT 0x02
|
|
#define CLRSEQ_SPLTINT 0x01
|
|
|
|
#define SWTIMER 0x0e
|
|
|
|
#define SNSCB_QOFF 0x10
|
|
|
|
#define SESCB_QOFF 0x12
|
|
|
|
#define SDSCB_QOFF 0x14
|
|
|
|
#define QOFF_CTLSTA 0x16
|
|
#define EMPTY_SCB_AVAIL 0x80
|
|
#define NEW_SCB_AVAIL 0x40
|
|
#define SDSCB_ROLLOVR 0x20
|
|
#define HS_MAILBOX_ACT 0x10
|
|
#define SCB_QSIZE 0x0f
|
|
#define SCB_QSIZE_16384 0x0c
|
|
#define SCB_QSIZE_8192 0x0b
|
|
#define SCB_QSIZE_4096 0x0a
|
|
#define SCB_QSIZE_2048 0x09
|
|
#define SCB_QSIZE_1024 0x08
|
|
#define SCB_QSIZE_512 0x07
|
|
#define SCB_QSIZE_256 0x06
|
|
#define SCB_QSIZE_128 0x05
|
|
#define SCB_QSIZE_64 0x04
|
|
#define SCB_QSIZE_32 0x03
|
|
#define SCB_QSIZE_16 0x02
|
|
#define SCB_QSIZE_8 0x01
|
|
#define SCB_QSIZE_4 0x00
|
|
|
|
#define INTCTL 0x18
|
|
#define SWTMINTMASK 0x80
|
|
#define SWTMINTEN 0x40
|
|
#define SWTIMER_START 0x20
|
|
#define AUTOCLRCMDINT 0x10
|
|
#define PCIINTEN 0x08
|
|
#define SCSIINTEN 0x04
|
|
#define SEQINTEN 0x02
|
|
#define SPLTINTEN 0x01
|
|
|
|
#define DFCNTRL 0x19
|
|
#define SCSIENWRDIS 0x40
|
|
#define SCSIENACK 0x20
|
|
#define DIRECTIONACK 0x04
|
|
#define FIFOFLUSHACK 0x02
|
|
#define DIRECTIONEN 0x01
|
|
|
|
#define DSCOMMAND0 0x19
|
|
#define CACHETHEN 0x80
|
|
#define DPARCKEN 0x40
|
|
#define MPARCKEN 0x20
|
|
#define EXTREQLCK 0x10
|
|
#define DISABLE_TWATE 0x02
|
|
#define CIOPARCKEN 0x01
|
|
|
|
#define DFSTATUS 0x1a
|
|
#define PRELOAD_AVAIL 0x80
|
|
#define PKT_PRELOAD_AVAIL 0x40
|
|
#define MREQPEND 0x10
|
|
#define HDONE 0x08
|
|
#define DFTHRESH 0x04
|
|
#define FIFOFULL 0x02
|
|
#define FIFOEMP 0x01
|
|
|
|
#define SG_CACHE_SHADOW 0x1b
|
|
#define ODD_SEG 0x04
|
|
#define LAST_SEG 0x02
|
|
#define LAST_SEG_DONE 0x01
|
|
|
|
#define ARBCTL 0x1b
|
|
#define RESET_HARB 0x80
|
|
#define RETRY_SWEN 0x08
|
|
#define USE_TIME 0x07
|
|
|
|
#define SG_CACHE_PRE 0x1b
|
|
|
|
#define LQIN 0x20
|
|
|
|
#define TYPEPTR 0x20
|
|
|
|
#define TAGPTR 0x21
|
|
|
|
#define LUNPTR 0x22
|
|
|
|
#define DATALENPTR 0x23
|
|
|
|
#define STATLENPTR 0x24
|
|
|
|
#define CMDLENPTR 0x25
|
|
|
|
#define ATTRPTR 0x26
|
|
|
|
#define FLAGPTR 0x27
|
|
|
|
#define CMDPTR 0x28
|
|
|
|
#define QNEXTPTR 0x29
|
|
|
|
#define IDPTR 0x2a
|
|
|
|
#define ABRTBYTEPTR 0x2b
|
|
|
|
#define ABRTBITPTR 0x2c
|
|
|
|
#define MAXCMDBYTES 0x2d
|
|
|
|
#define MAXCMD2RCV 0x2e
|
|
|
|
#define SHORTTHRESH 0x2f
|
|
|
|
#define LUNLEN 0x30
|
|
#define TLUNLEN 0xf0
|
|
#define ILUNLEN 0x0f
|
|
|
|
#define CDBLIMIT 0x31
|
|
|
|
#define MAXCMD 0x32
|
|
|
|
#define MAXCMDCNT 0x33
|
|
|
|
#define LQRSVD01 0x34
|
|
|
|
#define LQRSVD16 0x35
|
|
|
|
#define LQRSVD17 0x36
|
|
|
|
#define CMDRSVD0 0x37
|
|
|
|
#define LQCTL0 0x38
|
|
#define LQITARGCLT 0xc0
|
|
#define LQIINITGCLT 0x30
|
|
#define LQ0TARGCLT 0x0c
|
|
#define LQ0INITGCLT 0x03
|
|
|
|
#define LQCTL1 0x38
|
|
#define PCI2PCI 0x04
|
|
#define SINGLECMD 0x02
|
|
#define ABORTPENDING 0x01
|
|
|
|
#define SCSBIST0 0x39
|
|
#define GSBISTERR 0x40
|
|
#define GSBISTDONE 0x20
|
|
#define GSBISTRUN 0x10
|
|
#define OSBISTERR 0x04
|
|
#define OSBISTDONE 0x02
|
|
#define OSBISTRUN 0x01
|
|
|
|
#define LQCTL2 0x39
|
|
#define LQIRETRY 0x80
|
|
#define LQICONTINUE 0x40
|
|
#define LQITOIDLE 0x20
|
|
#define LQIPAUSE 0x10
|
|
#define LQORETRY 0x08
|
|
#define LQOCONTINUE 0x04
|
|
#define LQOTOIDLE 0x02
|
|
#define LQOPAUSE 0x01
|
|
|
|
#define SCSBIST1 0x3a
|
|
#define NTBISTERR 0x04
|
|
#define NTBISTDONE 0x02
|
|
#define NTBISTRUN 0x01
|
|
|
|
#define SCSISEQ0 0x3a
|
|
#define TEMODEO 0x80
|
|
#define ENSELO 0x40
|
|
#define ENARBO 0x20
|
|
#define FORCEBUSFREE 0x10
|
|
#define SCSIRSTO 0x01
|
|
|
|
#define SCSISEQ1 0x3b
|
|
|
|
#define SXFRCTL0 0x3c
|
|
#define DFON 0x80
|
|
#define DFPEXP 0x40
|
|
#define BIOSCANCELEN 0x10
|
|
#define SPIOEN 0x08
|
|
|
|
#define DLCOUNT 0x3c
|
|
|
|
#define BUSINITID 0x3c
|
|
|
|
#define SXFRCTL1 0x3d
|
|
#define BITBUCKET 0x80
|
|
#define ENSACHK 0x40
|
|
#define ENSPCHK 0x20
|
|
#define STIMESEL 0x18
|
|
#define ENSTIMER 0x04
|
|
#define ACTNEGEN 0x02
|
|
#define STPWEN 0x01
|
|
|
|
#define BUSTARGID 0x3e
|
|
|
|
#define SXFRCTL2 0x3e
|
|
#define AUTORSTDIS 0x10
|
|
#define CMDDMAEN 0x08
|
|
#define ASU 0x07
|
|
|
|
#define DFFSTAT 0x3f
|
|
#define CURRFIFO 0x03
|
|
#define FIFO1FREE 0x20
|
|
#define FIFO0FREE 0x10
|
|
#define CURRFIFO_NONE 0x03
|
|
#define CURRFIFO_1 0x01
|
|
#define CURRFIFO_0 0x00
|
|
|
|
#define SCSISIGO 0x40
|
|
#define CDO 0x80
|
|
#define IOO 0x40
|
|
#define MSGO 0x20
|
|
#define ATNO 0x10
|
|
#define SELO 0x08
|
|
#define BSYO 0x04
|
|
#define REQO 0x02
|
|
#define ACKO 0x01
|
|
|
|
#define MULTARGID 0x40
|
|
|
|
#define SCSISIGI 0x41
|
|
#define ATNI 0x10
|
|
#define SELI 0x08
|
|
#define BSYI 0x04
|
|
#define REQI 0x02
|
|
#define ACKI 0x01
|
|
|
|
#define SCSIPHASE 0x42
|
|
#define STATUS_PHASE 0x20
|
|
#define COMMAND_PHASE 0x10
|
|
#define MSG_IN_PHASE 0x08
|
|
#define MSG_OUT_PHASE 0x04
|
|
#define DATA_PHASE_MASK 0x03
|
|
#define DATA_IN_PHASE 0x02
|
|
#define DATA_OUT_PHASE 0x01
|
|
|
|
#define SCSIDAT0_IMG 0x43
|
|
|
|
#define SCSIDAT 0x44
|
|
|
|
#define SCSIBUS 0x46
|
|
|
|
#define TARGIDIN 0x48
|
|
#define CLKOUT 0x80
|
|
#define TARGID 0x0f
|
|
|
|
#define SELID 0x49
|
|
#define SELID_MASK 0xf0
|
|
#define ONEBIT 0x08
|
|
|
|
#define OPTIONMODE 0x4a
|
|
#define OPTIONMODE_DEFAULTS 0x02
|
|
#define BIOSCANCTL 0x80
|
|
#define AUTOACKEN 0x40
|
|
#define BIASCANCTL 0x20
|
|
#define BUSFREEREV 0x10
|
|
#define ENDGFORMCHK 0x04
|
|
#define AUTO_MSGOUT_DE 0x02
|
|
|
|
#define SBLKCTL 0x4a
|
|
#define DIAGLEDEN 0x80
|
|
#define DIAGLEDON 0x40
|
|
#define ENAB40 0x08
|
|
#define ENAB20 0x04
|
|
#define SELWIDE 0x02
|
|
|
|
#define CLRSINT0 0x4b
|
|
#define CLRSELDO 0x40
|
|
#define CLRSELDI 0x20
|
|
#define CLRSELINGO 0x10
|
|
#define CLRIOERR 0x08
|
|
#define CLROVERRUN 0x04
|
|
#define CLRSPIORDY 0x02
|
|
#define CLRARBDO 0x01
|
|
|
|
#define SSTAT0 0x4b
|
|
#define TARGET 0x80
|
|
#define SELDO 0x40
|
|
#define SELDI 0x20
|
|
#define SELINGO 0x10
|
|
#define IOERR 0x08
|
|
#define OVERRUN 0x04
|
|
#define SPIORDY 0x02
|
|
#define ARBDO 0x01
|
|
|
|
#define SIMODE0 0x4b
|
|
#define ENSELDO 0x40
|
|
#define ENSELDI 0x20
|
|
#define ENSELINGO 0x10
|
|
#define ENIOERR 0x08
|
|
#define ENOVERRUN 0x04
|
|
#define ENSPIORDY 0x02
|
|
#define ENARBDO 0x01
|
|
|
|
#define CLRSINT1 0x4c
|
|
#define CLRSELTIMEO 0x80
|
|
#define CLRATNO 0x40
|
|
#define CLRSCSIRSTI 0x20
|
|
#define CLRBUSFREE 0x08
|
|
#define CLRSCSIPERR 0x04
|
|
#define CLRSTRB2FAST 0x02
|
|
#define CLRREQINIT 0x01
|
|
|
|
#define SSTAT1 0x4c
|
|
#define SELTO 0x80
|
|
#define ATNTARG 0x40
|
|
#define SCSIRSTI 0x20
|
|
#define PHASEMIS 0x10
|
|
#define BUSFREE 0x08
|
|
#define SCSIPERR 0x04
|
|
#define STRB2FAST 0x02
|
|
#define REQINIT 0x01
|
|
|
|
#define SSTAT2 0x4d
|
|
#define BUSFREETIME 0xc0
|
|
#define NONPACKREQ 0x20
|
|
#define EXP_ACTIVE 0x10
|
|
#define BSYX 0x08
|
|
#define WIDE_RES 0x04
|
|
#define SDONE 0x02
|
|
#define DMADONE 0x01
|
|
#define BUSFREE_DFF1 0xc0
|
|
#define BUSFREE_DFF0 0x80
|
|
#define BUSFREE_LQO 0x40
|
|
|
|
#define SIMODE2 0x4d
|
|
#define ENWIDE_RES 0x04
|
|
#define ENSDONE 0x02
|
|
#define ENDMADONE 0x01
|
|
|
|
#define CLRSINT2 0x4d
|
|
#define CLRNONPACKREQ 0x20
|
|
#define CLRWIDE_RES 0x04
|
|
#define CLRSDONE 0x02
|
|
#define CLRDMADONE 0x01
|
|
|
|
#define PERRDIAG 0x4e
|
|
#define HIZERO 0x80
|
|
#define HIPERR 0x40
|
|
#define PREVPHASE 0x20
|
|
#define PARITYERR 0x10
|
|
#define AIPERR 0x08
|
|
#define CRCERR 0x04
|
|
#define DGFORMERR 0x02
|
|
#define DTERR 0x01
|
|
|
|
#define LQISTATE 0x4e
|
|
|
|
#define SOFFCNT 0x4f
|
|
|
|
#define LQOSTATE 0x4f
|
|
|
|
#define LQISTAT0 0x50
|
|
#define LQIATNQAS 0x20
|
|
#define LQICRCT1 0x10
|
|
#define LQICRCT2 0x08
|
|
#define LQIBADLQT 0x04
|
|
#define LQIATNLQ 0x02
|
|
#define LQIATNCMD 0x01
|
|
|
|
#define CLRLQIINT0 0x50
|
|
#define CLRLQIATNQAS 0x20
|
|
#define CLRLQICRCT1 0x10
|
|
#define CLRLQICRCT2 0x08
|
|
#define CLRLQIBADLQT 0x04
|
|
#define CLRLQIATNLQ 0x02
|
|
#define CLRLQIATNCMD 0x01
|
|
|
|
#define LQIMODE0 0x50
|
|
#define ENLQIATNQASK 0x20
|
|
#define ENLQICRCT1 0x10
|
|
#define ENLQICRCT2 0x08
|
|
#define ENLQIBADLQT 0x04
|
|
#define ENLQIATNLQ 0x02
|
|
#define ENLQIATNCMD 0x01
|
|
|
|
#define LQIMODE1 0x51
|
|
#define ENLQIPHASE_LQ 0x80
|
|
#define ENLQIPHASE_NLQ 0x40
|
|
#define ENLIQABORT 0x20
|
|
#define ENLQICRCI_LQ 0x10
|
|
#define ENLQICRCI_NLQ 0x08
|
|
#define ENLQIBADLQI 0x04
|
|
#define ENLQIOVERI_LQ 0x02
|
|
#define ENLQIOVERI_NLQ 0x01
|
|
|
|
#define LQISTAT1 0x51
|
|
#define LQIPHASE_LQ 0x80
|
|
#define LQIPHASE_NLQ 0x40
|
|
#define LQIABORT 0x20
|
|
#define LQICRCI_LQ 0x10
|
|
#define LQICRCI_NLQ 0x08
|
|
#define LQIBADLQI 0x04
|
|
#define LQIOVERI_LQ 0x02
|
|
#define LQIOVERI_NLQ 0x01
|
|
|
|
#define CLRLQIINT1 0x51
|
|
#define CLRLQIPHASE_LQ 0x80
|
|
#define CLRLQIPHASE_NLQ 0x40
|
|
#define CLRLIQABORT 0x20
|
|
#define CLRLQICRCI_LQ 0x10
|
|
#define CLRLQICRCI_NLQ 0x08
|
|
#define CLRLQIBADLQI 0x04
|
|
#define CLRLQIOVERI_LQ 0x02
|
|
#define CLRLQIOVERI_NLQ 0x01
|
|
|
|
#define LQISTAT2 0x52
|
|
#define PACKETIZED 0x80
|
|
#define LQIPHASE_OUTPKT 0x40
|
|
#define LQIWORKONLQ 0x20
|
|
#define LQIWAITFIFO 0x10
|
|
#define LQISTOPPKT 0x08
|
|
#define LQISTOPLQ 0x04
|
|
#define LQISTOPCMD 0x02
|
|
#define LQIGSAVAIL 0x01
|
|
|
|
#define SSTAT3 0x53
|
|
#define NTRAMPERR 0x02
|
|
#define OSRAMPERR 0x01
|
|
|
|
#define SIMODE3 0x53
|
|
#define ENNTRAMPERR 0x02
|
|
#define ENOSRAMPERR 0x01
|
|
|
|
#define CLRSINT3 0x53
|
|
#define CLRNTRAMPERR 0x02
|
|
#define CLROSRAMPERR 0x01
|
|
|
|
#define LQOSTAT0 0x54
|
|
#define LQOTARGSCBPERR 0x10
|
|
#define LQOSTOPT2 0x08
|
|
#define LQOATNLQ 0x04
|
|
#define LQOATNPKT 0x02
|
|
#define LQOTCRC 0x01
|
|
|
|
#define CLRLQOINT0 0x54
|
|
#define CLRLQOTARGSCBPERR 0x10
|
|
#define CLRLQOSTOPT2 0x08
|
|
#define CLRLQOATNLQ 0x04
|
|
#define CLRLQOATNPKT 0x02
|
|
#define CLRLQOTCRC 0x01
|
|
|
|
#define LQOMODE0 0x54
|
|
#define ENLQOTARGSCBPERR 0x10
|
|
#define ENLQOSTOPT2 0x08
|
|
#define ENLQOATNLQ 0x04
|
|
#define ENLQOATNPKT 0x02
|
|
#define ENLQOTCRC 0x01
|
|
|
|
#define LQOMODE1 0x55
|
|
#define ENLQOINITSCBPERR 0x10
|
|
#define ENLQOSTOPI2 0x08
|
|
#define ENLQOBADQAS 0x04
|
|
#define ENLQOBUSFREE 0x02
|
|
#define ENLQOPHACHGINPKT 0x01
|
|
|
|
#define LQOSTAT1 0x55
|
|
#define LQOINITSCBPERR 0x10
|
|
#define LQOSTOPI2 0x08
|
|
#define LQOBADQAS 0x04
|
|
#define LQOBUSFREE 0x02
|
|
#define LQOPHACHGINPKT 0x01
|
|
|
|
#define CLRLQOINT1 0x55
|
|
#define CLRLQOINITSCBPERR 0x10
|
|
#define CLRLQOSTOPI2 0x08
|
|
#define CLRLQOBADQAS 0x04
|
|
#define CLRLQOBUSFREE 0x02
|
|
#define CLRLQOPHACHGINPKT 0x01
|
|
|
|
#define LQOSTAT2 0x56
|
|
#define LQOPKT 0xe0
|
|
#define LQOWAITFIFO 0x10
|
|
#define LQOPHACHGOUTPKT 0x02
|
|
#define LQOSTOP0 0x01
|
|
|
|
#define OS_SPACE_CNT 0x56
|
|
|
|
#define SIMODE1 0x57
|
|
#define ENSELTIMO 0x80
|
|
#define ENATNTARG 0x40
|
|
#define ENSCSIRST 0x20
|
|
#define ENPHASEMIS 0x10
|
|
#define ENBUSFREE 0x08
|
|
#define ENSCSIPERR 0x04
|
|
#define ENSTRB2FAST 0x02
|
|
#define ENREQINIT 0x01
|
|
|
|
#define GSFIFO 0x58
|
|
|
|
#define DFFSXFRCTL 0x5a
|
|
#define DFFBITBUCKET 0x08
|
|
#define CLRSHCNT 0x04
|
|
#define CLRCHN 0x02
|
|
#define RSTCHN 0x01
|
|
|
|
#define LQOSCSCTL 0x5a
|
|
#define LQOH2A_VERSION 0x80
|
|
#define LQOBUSETDLY 0x40
|
|
#define LQONOHOLDLACK 0x02
|
|
#define LQONOCHKOVER 0x01
|
|
|
|
#define NEXTSCB 0x5a
|
|
|
|
#define CLRSEQINTSRC 0x5b
|
|
#define CLRCTXTDONE 0x40
|
|
#define CLRSAVEPTRS 0x20
|
|
#define CLRCFG4DATA 0x10
|
|
#define CLRCFG4ISTAT 0x08
|
|
#define CLRCFG4TSTAT 0x04
|
|
#define CLRCFG4ICMD 0x02
|
|
#define CLRCFG4TCMD 0x01
|
|
|
|
#define SEQINTSRC 0x5b
|
|
#define CTXTDONE 0x40
|
|
#define SAVEPTRS 0x20
|
|
#define CFG4DATA 0x10
|
|
#define CFG4ISTAT 0x08
|
|
#define CFG4TSTAT 0x04
|
|
#define CFG4ICMD 0x02
|
|
#define CFG4TCMD 0x01
|
|
|
|
#define CURRSCB 0x5c
|
|
|
|
#define SEQIMODE 0x5c
|
|
#define ENCTXTDONE 0x40
|
|
#define ENSAVEPTRS 0x20
|
|
#define ENCFG4DATA 0x10
|
|
#define ENCFG4ISTAT 0x08
|
|
#define ENCFG4TSTAT 0x04
|
|
#define ENCFG4ICMD 0x02
|
|
#define ENCFG4TCMD 0x01
|
|
|
|
#define MDFFSTAT 0x5d
|
|
#define SHCNTNEGATIVE 0x40
|
|
#define SHCNTMINUS1 0x20
|
|
#define LASTSDONE 0x10
|
|
#define SHVALID 0x08
|
|
#define DLZERO 0x04
|
|
#define DATAINFIFO 0x02
|
|
#define FIFOFREE 0x01
|
|
|
|
#define CRCCONTROL 0x5d
|
|
#define CRCVALCHKEN 0x40
|
|
|
|
#define DFFTAG 0x5e
|
|
|
|
#define LASTSCB 0x5e
|
|
|
|
#define SCSITEST 0x5e
|
|
#define CNTRTEST 0x08
|
|
#define SEL_TXPLL_DEBUG 0x04
|
|
|
|
#define IOPDNCTL 0x5f
|
|
#define DISABLE_OE 0x80
|
|
#define PDN_IDIST 0x04
|
|
#define PDN_DIFFSENSE 0x01
|
|
|
|
#define SHADDR 0x60
|
|
|
|
#define NEGOADDR 0x60
|
|
|
|
#define DGRPCRCI 0x60
|
|
|
|
#define NEGPERIOD 0x61
|
|
|
|
#define PACKCRCI 0x62
|
|
|
|
#define NEGOFFSET 0x62
|
|
|
|
#define NEGPPROPTS 0x63
|
|
#define PPROPT_PACE 0x08
|
|
#define PPROPT_QAS 0x04
|
|
#define PPROPT_DT 0x02
|
|
#define PPROPT_IUT 0x01
|
|
|
|
#define NEGCONOPTS 0x64
|
|
#define ENSNAPSHOT 0x40
|
|
#define RTI_WRTDIS 0x20
|
|
#define RTI_OVRDTRN 0x10
|
|
#define ENSLOWCRC 0x08
|
|
#define ENAUTOATNI 0x04
|
|
#define ENAUTOATNO 0x02
|
|
#define WIDEXFER 0x01
|
|
|
|
#define ANNEXCOL 0x65
|
|
|
|
#define ANNEXDAT 0x66
|
|
|
|
#define SCSCHKN 0x66
|
|
#define BIDICHKDIS 0x80
|
|
#define STSELSKIDDIS 0x40
|
|
#define CURRFIFODEF 0x20
|
|
#define WIDERESEN 0x10
|
|
#define SDONEMSKDIS 0x08
|
|
#define DFFACTCLR 0x04
|
|
#define SHVALIDSTDIS 0x02
|
|
#define LSTSGCLRDIS 0x01
|
|
|
|
#define IOWNID 0x67
|
|
|
|
#define PLL960CTL0 0x68
|
|
|
|
#define SHCNT 0x68
|
|
|
|
#define TOWNID 0x69
|
|
|
|
#define PLL960CTL1 0x69
|
|
|
|
#define PLL960CNT0 0x6a
|
|
|
|
#define XSIG 0x6a
|
|
|
|
#define SELOID 0x6b
|
|
|
|
#define PLL400CTL0 0x6c
|
|
#define PLL_VCOSEL 0x80
|
|
#define PLL_PWDN 0x40
|
|
#define PLL_NS 0x30
|
|
#define PLL_ENLUD 0x08
|
|
#define PLL_ENLPF 0x04
|
|
#define PLL_DLPF 0x02
|
|
#define PLL_ENFBM 0x01
|
|
|
|
#define FAIRNESS 0x6c
|
|
|
|
#define PLL400CTL1 0x6d
|
|
#define PLL_CNTEN 0x80
|
|
#define PLL_CNTCLR 0x40
|
|
#define PLL_RST 0x01
|
|
|
|
#define UNFAIRNESS 0x6e
|
|
|
|
#define PLL400CNT0 0x6e
|
|
|
|
#define HADDR 0x70
|
|
|
|
#define PLLDELAY 0x70
|
|
#define SPLIT_DROP_REQ 0x80
|
|
|
|
#define HODMAADR 0x70
|
|
|
|
#define HODMACNT 0x78
|
|
|
|
#define HCNT 0x78
|
|
|
|
#define HODMAEN 0x7a
|
|
|
|
#define SCBHADDR 0x7c
|
|
|
|
#define SGHADDR 0x7c
|
|
|
|
#define SCBHCNT 0x84
|
|
|
|
#define SGHCNT 0x84
|
|
|
|
#define DFF_THRSH 0x88
|
|
#define WR_DFTHRSH 0x70
|
|
#define RD_DFTHRSH 0x07
|
|
#define WR_DFTHRSH_MAX 0x70
|
|
#define WR_DFTHRSH_90 0x60
|
|
#define WR_DFTHRSH_85 0x50
|
|
#define WR_DFTHRSH_75 0x40
|
|
#define WR_DFTHRSH_63 0x30
|
|
#define WR_DFTHRSH_50 0x20
|
|
#define WR_DFTHRSH_25 0x10
|
|
#define RD_DFTHRSH_MAX 0x07
|
|
#define RD_DFTHRSH_90 0x06
|
|
#define RD_DFTHRSH_85 0x05
|
|
#define RD_DFTHRSH_75 0x04
|
|
#define RD_DFTHRSH_63 0x03
|
|
#define RD_DFTHRSH_50 0x02
|
|
#define RD_DFTHRSH_25 0x01
|
|
#define RD_DFTHRSH_MIN 0x00
|
|
#define WR_DFTHRSH_MIN 0x00
|
|
|
|
#define ROMADDR 0x8a
|
|
|
|
#define ROMCNTRL 0x8d
|
|
#define ROMOP 0xe0
|
|
#define ROMSPD 0x18
|
|
#define REPEAT 0x02
|
|
#define RDY 0x01
|
|
|
|
#define ROMDATA 0x8e
|
|
|
|
#define CMCRXMSG0 0x90
|
|
|
|
#define ROENABLE 0x90
|
|
#define MSIROEN 0x20
|
|
#define OVLYROEN 0x10
|
|
#define CMCROEN 0x08
|
|
#define SGROEN 0x04
|
|
#define DCH1ROEN 0x02
|
|
#define DCH0ROEN 0x01
|
|
|
|
#define OVLYRXMSG0 0x90
|
|
|
|
#define DCHRXMSG0 0x90
|
|
|
|
#define OVLYRXMSG1 0x91
|
|
|
|
#define NSENABLE 0x91
|
|
#define MSINSEN 0x20
|
|
#define OVLYNSEN 0x10
|
|
#define CMCNSEN 0x08
|
|
#define SGNSEN 0x04
|
|
#define DCH1NSEN 0x02
|
|
#define DCH0NSEN 0x01
|
|
|
|
#define CMCRXMSG1 0x91
|
|
|
|
#define DCHRXMSG1 0x91
|
|
|
|
#define DCHRXMSG2 0x92
|
|
|
|
#define CMCRXMSG2 0x92
|
|
|
|
#define OST 0x92
|
|
|
|
#define OVLYRXMSG2 0x92
|
|
|
|
#define DCHRXMSG3 0x93
|
|
|
|
#define OVLYRXMSG3 0x93
|
|
|
|
#define CMCRXMSG3 0x93
|
|
|
|
#define PCIXCTL 0x93
|
|
#define SERRPULSE 0x80
|
|
#define UNEXPSCIEN 0x20
|
|
#define SPLTSMADIS 0x10
|
|
#define SPLTSTADIS 0x08
|
|
#define SRSPDPEEN 0x04
|
|
#define TSCSERREN 0x02
|
|
#define CMPABCDIS 0x01
|
|
|
|
#define OVLYSEQBCNT 0x94
|
|
|
|
#define DCHSEQBCNT 0x94
|
|
|
|
#define CMCSEQBCNT 0x94
|
|
|
|
#define CMCSPLTSTAT0 0x96
|
|
|
|
#define DCHSPLTSTAT0 0x96
|
|
|
|
#define OVLYSPLTSTAT0 0x96
|
|
|
|
#define CMCSPLTSTAT1 0x97
|
|
|
|
#define OVLYSPLTSTAT1 0x97
|
|
|
|
#define DCHSPLTSTAT1 0x97
|
|
|
|
#define SGRXMSG0 0x98
|
|
#define CDNUM 0xf8
|
|
#define CFNUM 0x07
|
|
|
|
#define SLVSPLTOUTADR0 0x98
|
|
#define LOWER_ADDR 0x7f
|
|
|
|
#define SGRXMSG1 0x99
|
|
#define CBNUM 0xff
|
|
|
|
#define SLVSPLTOUTADR1 0x99
|
|
#define REQ_DNUM 0xf8
|
|
#define REQ_FNUM 0x07
|
|
|
|
#define SGRXMSG2 0x9a
|
|
#define MINDEX 0xff
|
|
|
|
#define SLVSPLTOUTADR2 0x9a
|
|
#define REQ_BNUM 0xff
|
|
|
|
#define SGRXMSG3 0x9b
|
|
#define MCLASS 0x0f
|
|
|
|
#define SLVSPLTOUTADR3 0x9b
|
|
#define TAG_NUM 0x1f
|
|
#define RLXORD 0x10
|
|
|
|
#define SGSEQBCNT 0x9c
|
|
|
|
#define SLVSPLTOUTATTR0 0x9c
|
|
#define LOWER_BCNT 0xff
|
|
|
|
#define SLVSPLTOUTATTR1 0x9d
|
|
#define CMPLT_DNUM 0xf8
|
|
#define CMPLT_FNUM 0x07
|
|
|
|
#define SLVSPLTOUTATTR2 0x9e
|
|
#define CMPLT_BNUM 0xff
|
|
|
|
#define SGSPLTSTAT0 0x9e
|
|
#define STAETERM 0x80
|
|
#define SCBCERR 0x40
|
|
#define SCADERR 0x20
|
|
#define SCDATBUCKET 0x10
|
|
#define CNTNOTCMPLT 0x08
|
|
#define RXOVRUN 0x04
|
|
#define RXSCEMSG 0x02
|
|
#define RXSPLTRSP 0x01
|
|
|
|
#define SGSPLTSTAT1 0x9f
|
|
#define RXDATABUCKET 0x01
|
|
|
|
#define SFUNCT 0x9f
|
|
#define TEST_GROUP 0xf0
|
|
#define TEST_NUM 0x0f
|
|
|
|
#define DF0PCISTAT 0xa0
|
|
|
|
#define REG0 0xa0
|
|
|
|
#define DF1PCISTAT 0xa1
|
|
|
|
#define SGPCISTAT 0xa2
|
|
|
|
#define REG1 0xa2
|
|
|
|
#define CMCPCISTAT 0xa3
|
|
|
|
#define OVLYPCISTAT 0xa4
|
|
#define SCAAPERR 0x08
|
|
#define RDPERR 0x04
|
|
|
|
#define REG_ISR 0xa4
|
|
|
|
#define SG_STATE 0xa6
|
|
#define FETCH_INPROG 0x04
|
|
#define LOADING_NEEDED 0x02
|
|
#define SEGS_AVAIL 0x01
|
|
|
|
#define MSIPCISTAT 0xa6
|
|
#define RMA 0x20
|
|
#define RTA 0x10
|
|
#define CLRPENDMSI 0x08
|
|
#define DPR 0x01
|
|
|
|
#define TARGPCISTAT 0xa7
|
|
#define DPE 0x80
|
|
#define SSE 0x40
|
|
#define STA 0x08
|
|
#define TWATERR 0x02
|
|
|
|
#define DATA_COUNT_ODD 0xa7
|
|
|
|
#define SCBPTR 0xa8
|
|
|
|
#define CCSCBACNT 0xab
|
|
|
|
#define SCBAUTOPTR 0xab
|
|
#define AUSCBPTR_EN 0x80
|
|
#define SCBPTR_ADDR 0x38
|
|
#define SCBPTR_OFF 0x07
|
|
|
|
#define CCSGADDR 0xac
|
|
|
|
#define CCSCBADR_BK 0xac
|
|
|
|
#define CCSCBADDR 0xac
|
|
|
|
#define CMC_RAMBIST 0xad
|
|
#define SG_ELEMENT_SIZE 0x80
|
|
#define SCBRAMBIST_FAIL 0x40
|
|
#define SG_BIST_FAIL 0x20
|
|
#define SG_BIST_EN 0x10
|
|
#define CMC_BUFFER_BIST_FAIL 0x02
|
|
#define CMC_BUFFER_BIST_EN 0x01
|
|
|
|
#define CCSCBCTL 0xad
|
|
#define CCSCBDONE 0x80
|
|
#define ARRDONE 0x40
|
|
#define CCARREN 0x10
|
|
#define CCSCBEN 0x08
|
|
#define CCSCBDIR 0x04
|
|
#define CCSCBRESET 0x01
|
|
|
|
#define CCSGCTL 0xad
|
|
#define CCSGEN 0x0c
|
|
#define CCSGDONE 0x80
|
|
#define SG_CACHE_AVAIL 0x10
|
|
#define CCSGENACK 0x08
|
|
#define SG_FETCH_REQ 0x02
|
|
#define CCSGRESET 0x01
|
|
|
|
#define CCSGRAM 0xb0
|
|
|
|
#define FLEXADR 0xb0
|
|
|
|
#define CCSCBRAM 0xb0
|
|
|
|
#define FLEXCNT 0xb3
|
|
|
|
#define FLEXDMASTAT 0xb5
|
|
#define FLEXDMAERR 0x02
|
|
#define FLEXDMADONE 0x01
|
|
|
|
#define FLEXDATA 0xb6
|
|
|
|
#define BRDDAT 0xb8
|
|
|
|
#define BRDCTL 0xb9
|
|
#define FLXARBACK 0x80
|
|
#define FLXARBREQ 0x40
|
|
#define BRDADDR 0x38
|
|
#define BRDEN 0x04
|
|
#define BRDRW 0x02
|
|
#define BRDSTB 0x01
|
|
|
|
#define SEEADR 0xba
|
|
|
|
#define SEEDAT 0xbc
|
|
|
|
#define SEECTL 0xbe
|
|
#define SEEOP_WALL 0x40
|
|
#define SEEOP_EWEN 0x40
|
|
#define SEEOP_EWDS 0x40
|
|
#define SEEOPCODE 0x70
|
|
#define SEERST 0x02
|
|
#define SEESTART 0x01
|
|
#define SEEOP_ERASE 0x70
|
|
#define SEEOP_READ 0x60
|
|
#define SEEOP_WRITE 0x50
|
|
#define SEEOP_ERAL 0x40
|
|
|
|
#define SEESTAT 0xbe
|
|
#define INIT_DONE 0x80
|
|
#define LDALTID_L 0x08
|
|
#define SEEARBACK 0x04
|
|
#define SEEBUSY 0x02
|
|
|
|
#define SCBCNT 0xbf
|
|
|
|
#define DFWADDR 0xc0
|
|
|
|
#define DSPFLTRCTL 0xc0
|
|
#define FLTRDISABLE 0x20
|
|
#define EDGESENSE 0x10
|
|
#define DSPFCNTSEL 0x0f
|
|
|
|
#define DSPDATACTL 0xc1
|
|
#define BYPASSENAB 0x80
|
|
#define DESQDIS 0x10
|
|
#define RCVROFFSTDIS 0x04
|
|
#define XMITOFFSTDIS 0x02
|
|
|
|
#define DFRADDR 0xc2
|
|
|
|
#define DSPREQCTL 0xc2
|
|
#define MANREQCTL 0xc0
|
|
#define MANREQDLY 0x3f
|
|
|
|
#define DSPACKCTL 0xc3
|
|
#define MANACKCTL 0xc0
|
|
#define MANACKDLY 0x3f
|
|
|
|
#define DFDAT 0xc4
|
|
|
|
#define DSPSELECT 0xc4
|
|
#define AUTOINCEN 0x80
|
|
#define DSPSEL 0x1f
|
|
|
|
#define WRTBIASCTL 0xc5
|
|
#define AUTOXBCDIS 0x80
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|
#define XMITMANVAL 0x3f
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#define RCVRBIOSCTL 0xc6
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#define AUTORBCDIS 0x80
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#define RCVRMANVAL 0x3f
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#define WRTBIASCALC 0xc7
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#define RCVRBIASCALC 0xc8
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#define DFPTRS 0xc8
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#define SKEWCALC 0xc9
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#define DFBKPTR 0xc9
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#define DFDBCTL 0xcb
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#define DFF_CIO_WR_RDY 0x20
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#define DFF_CIO_RD_RDY 0x10
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#define DFF_DIR_ERR 0x08
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#define DFF_RAMBIST_FAIL 0x04
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#define DFF_RAMBIST_DONE 0x02
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#define DFF_RAMBIST_EN 0x01
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#define DFSCNT 0xcc
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#define DFBCNT 0xce
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#define OVLYADDR 0xd4
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#define SEQCTL0 0xd6
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#define PERRORDIS 0x80
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#define PAUSEDIS 0x40
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#define FAILDIS 0x20
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#define FASTMODE 0x10
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#define BRKADRINTEN 0x08
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#define STEP 0x04
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#define SEQRESET 0x02
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#define LOADRAM 0x01
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#define SEQCTL1 0xd7
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#define OVRLAY_DATA_CHK 0x08
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#define RAMBIST_DONE 0x04
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#define RAMBIST_FAIL 0x02
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#define RAMBIST_EN 0x01
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#define FLAGS 0xd8
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#define ZERO 0x02
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#define CARRY 0x01
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#define SEQINTCTL 0xd9
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#define INTVEC1DSL 0x80
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#define INT1_CONTEXT 0x20
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#define SCS_SEQ_INT1M1 0x10
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#define SCS_SEQ_INT1M0 0x08
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#define INTMASK2 0x04
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#define INTMASK1 0x02
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#define IRET 0x01
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#define SEQRAM 0xda
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#define PRGMCNT 0xde
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#define ACCUM 0xe0
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#define SINDEX 0xe2
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#define DINDEX 0xe4
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#define BRKADDR0 0xe6
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#define BRKADDR1 0xe6
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#define BRKDIS 0x80
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#define ALLONES 0xe8
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#define ALLZEROS 0xea
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#define NONE 0xea
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#define SINDIR 0xec
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#define DINDIR 0xed
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#define FUNCTION1 0xf0
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#define STACK 0xf2
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#define INTVEC1_ADDR 0xf4
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#define CURADDR 0xf4
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#define LASTADDR 0xf6
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#define INTVEC2_ADDR 0xf6
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#define LONGJMP_ADDR 0xf8
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#define ACCUM_SAVE 0xfa
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#define WAITING_SCB_TAILS 0x100
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#define AHD_PCI_CONFIG_BASE 0x100
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#define SRAM_BASE 0x100
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#define WAITING_TID_HEAD 0x120
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#define WAITING_TID_TAIL 0x122
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#define NEXT_QUEUED_SCB_ADDR 0x124
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#define COMPLETE_SCB_HEAD 0x128
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#define COMPLETE_SCB_DMAINPROG_HEAD 0x12a
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#define COMPLETE_DMA_SCB_HEAD 0x12c
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#define COMPLETE_DMA_SCB_TAIL 0x12e
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#define COMPLETE_ON_QFREEZE_HEAD 0x130
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#define QFREEZE_COUNT 0x132
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#define KERNEL_QFREEZE_COUNT 0x134
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#define SAVED_MODE 0x136
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#define MSG_OUT 0x137
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#define DMAPARAMS 0x138
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#define PRELOADEN 0x80
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#define WIDEODD 0x40
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#define SCSIEN 0x20
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#define SDMAEN 0x10
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#define SDMAENACK 0x10
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#define HDMAEN 0x08
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#define HDMAENACK 0x08
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#define DIRECTION 0x04
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#define FIFOFLUSH 0x02
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#define FIFORESET 0x01
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#define SEQ_FLAGS 0x139
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#define NOT_IDENTIFIED 0x80
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#define NO_CDB_SENT 0x40
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#define TARGET_CMD_IS_TAGGED 0x40
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#define DPHASE 0x20
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#define TARG_CMD_PENDING 0x10
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#define CMDPHASE_PENDING 0x08
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#define DPHASE_PENDING 0x04
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#define SPHASE_PENDING 0x02
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#define NO_DISCONNECT 0x01
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#define SAVED_SCSIID 0x13a
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#define SAVED_LUN 0x13b
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#define LASTPHASE 0x13c
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#define PHASE_MASK 0xe0
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#define CDI 0x80
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#define IOI 0x40
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#define MSGI 0x20
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#define P_BUSFREE 0x01
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#define P_MESGIN 0xe0
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#define P_STATUS 0xc0
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#define P_MESGOUT 0xa0
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#define P_COMMAND 0x80
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#define P_DATAIN_DT 0x60
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#define P_DATAIN 0x40
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#define P_DATAOUT_DT 0x20
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#define P_DATAOUT 0x00
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#define QOUTFIFO_ENTRY_VALID_TAG 0x13d
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#define KERNEL_TQINPOS 0x13e
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#define TQINPOS 0x13f
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#define SHARED_DATA_ADDR 0x140
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#define QOUTFIFO_NEXT_ADDR 0x144
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#define ARG_1 0x148
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#define RETURN_1 0x148
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#define SEND_MSG 0x80
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#define SEND_SENSE 0x40
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#define SEND_REJ 0x20
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#define MSGOUT_PHASEMIS 0x10
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#define EXIT_MSG_LOOP 0x08
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#define CONT_MSG_LOOP_WRITE 0x04
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#define CONT_MSG_LOOP_READ 0x03
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#define CONT_MSG_LOOP_TARG 0x02
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#define ARG_2 0x149
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#define RETURN_2 0x149
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#define LAST_MSG 0x14a
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#define SCSISEQ_TEMPLATE 0x14b
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#define MANUALCTL 0x40
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#define ENSELI 0x20
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#define ENRSELI 0x10
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#define MANUALP 0x0c
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#define ENAUTOATNP 0x02
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#define ALTSTIM 0x01
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#define INITIATOR_TAG 0x14c
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#define SEQ_FLAGS2 0x14d
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#define SELECTOUT_QFROZEN 0x04
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#define TARGET_MSG_PENDING 0x02
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#define PENDING_MK_MESSAGE 0x01
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#define ALLOCFIFO_SCBPTR 0x14e
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#define INT_COALESCING_TIMER 0x150
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#define INT_COALESCING_MAXCMDS 0x152
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#define INT_COALESCING_MINCMDS 0x153
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#define CMDS_PENDING 0x154
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#define INT_COALESCING_CMDCOUNT 0x156
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#define LOCAL_HS_MAILBOX 0x157
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#define CMDSIZE_TABLE 0x158
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#define MK_MESSAGE_SCB 0x160
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#define MK_MESSAGE_SCSIID 0x162
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#define SCB_BASE 0x180
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#define SCB_RESIDUAL_DATACNT 0x180
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#define SCB_CDB_STORE 0x180
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#define SCB_HOST_CDB_PTR 0x180
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#define SCB_RESIDUAL_SGPTR 0x184
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#define SG_ADDR_MASK 0xf8
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#define SG_OVERRUN_RESID 0x02
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#define SCB_SCSI_STATUS 0x188
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#define SCB_HOST_CDB_LEN 0x188
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#define SCB_TARGET_PHASES 0x189
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#define SCB_TARGET_DATA_DIR 0x18a
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#define SCB_TARGET_ITAG 0x18b
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#define SCB_SENSE_BUSADDR 0x18c
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#define SCB_NEXT_COMPLETE 0x18c
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#define SCB_TAG 0x190
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#define SCB_FIFO_USE_COUNT 0x190
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#define SCB_CONTROL 0x192
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#define TARGET_SCB 0x80
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#define DISCENB 0x40
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#define TAG_ENB 0x20
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#define MK_MESSAGE 0x10
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#define STATUS_RCVD 0x08
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#define DISCONNECTED 0x04
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#define SCB_TAG_TYPE 0x03
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#define SCB_SCSIID 0x193
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#define TID 0xf0
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#define OID 0x0f
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#define SCB_LUN 0x194
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#define LID 0xff
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#define SCB_TASK_ATTRIBUTE 0x195
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#define SCB_XFERLEN_ODD 0x01
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#define SCB_CDB_LEN 0x196
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#define SCB_CDB_LEN_PTR 0x80
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#define SCB_TASK_MANAGEMENT 0x197
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#define SCB_DATAPTR 0x198
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#define SCB_DATACNT 0x1a0
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#define SG_LAST_SEG 0x80
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#define SG_HIGH_ADDR_BITS 0x7f
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#define SCB_SGPTR 0x1a4
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#define SG_STATUS_VALID 0x04
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#define SG_FULL_RESID 0x02
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#define SG_LIST_NULL 0x01
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#define SCB_BUSADDR 0x1a8
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#define SCB_NEXT 0x1ac
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#define SCB_NEXT_SCB_BUSADDR 0x1ac
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#define SCB_NEXT2 0x1ae
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#define SCB_SPARE 0x1b0
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#define SCB_PKT_LUN 0x1b0
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#define SCB_DISCONNECTED_LISTS 0x1b8
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#define AHD_TIMER_MAX_US 0x18ffe7
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#define AHD_TIMER_MAX_TICKS 0xffff
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#define AHD_SENSE_BUFSIZE 0x100
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#define BUS_8_BIT 0x00
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#define TARGET_CMD_CMPLT 0xfe
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#define SEEOP_WRAL_ADDR 0x40
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#define AHD_AMPLITUDE_DEF 0x07
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#define AHD_PRECOMP_CUTBACK_37 0x07
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#define AHD_PRECOMP_SHIFT 0x00
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#define AHD_ANNEXCOL_PRECOMP_SLEW 0x04
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#define AHD_TIMER_US_PER_TICK 0x19
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#define SCB_TRANSFER_SIZE_FULL_LUN 0x38
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#define STATUS_QUEUE_FULL 0x28
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#define STATUS_BUSY 0x08
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#define MAX_OFFSET_NON_PACED 0x7f
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#define MAX_OFFSET_PACED 0xfe
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#define BUS_32_BIT 0x02
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#define CCSGADDR_MAX 0x80
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#define TID_SHIFT 0x04
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#define MK_MESSAGE_BIT_OFFSET 0x04
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#define WRTBIASCTL_HP_DEFAULT 0x00
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#define SEEOP_EWDS_ADDR 0x00
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#define AHD_AMPLITUDE_SHIFT 0x00
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#define AHD_AMPLITUDE_MASK 0x07
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#define AHD_ANNEXCOL_AMPLITUDE 0x06
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#define AHD_SLEWRATE_DEF_REVA 0x08
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#define AHD_SLEWRATE_SHIFT 0x03
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#define AHD_SLEWRATE_MASK 0x78
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#define AHD_PRECOMP_CUTBACK_29 0x06
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#define AHD_NUM_PER_DEV_ANNEXCOLS 0x04
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#define B_CURRFIFO_0 0x02
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#define LUNLEN_SINGLE_LEVEL_LUN 0x0f
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#define NVRAM_SCB_OFFSET 0x2c
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#define STATUS_PKT_SENSE 0xff
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#define CMD_GROUP_CODE_SHIFT 0x05
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#define MAX_OFFSET_PACED_BUG 0x7f
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#define STIMESEL_BUG_ADJ 0x08
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#define STIMESEL_MIN 0x18
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#define STIMESEL_SHIFT 0x03
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#define CCSGRAM_MAXSEGS 0x10
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#define INVALID_ADDR 0x80
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#define SEEOP_ERAL_ADDR 0x80
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#define AHD_SLEWRATE_DEF_REVB 0x08
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#define AHD_PRECOMP_CUTBACK_17 0x04
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#define AHD_PRECOMP_MASK 0x07
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#define SRC_MODE_SHIFT 0x00
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#define PKT_OVERRUN_BUFSIZE 0x200
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#define SCB_TRANSFER_SIZE_1BYTE_LUN 0x30
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#define TARGET_DATA_IN 0x01
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#define HOST_MSG 0xff
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#define MAX_OFFSET 0xfe
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#define BUS_16_BIT 0x01
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#define CCSCBADDR_MAX 0x80
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#define NUMDSPS 0x14
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#define SEEOP_EWEN_ADDR 0xc0
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#define AHD_ANNEXCOL_PER_DEV0 0x04
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#define DST_MODE_SHIFT 0x04
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/* Downloaded Constant Definitions */
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#define CACHELINE_MASK 0x07
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#define SCB_TRANSFER_SIZE 0x06
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#define PKT_OVERRUN_BUFOFFSET 0x05
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#define SG_SIZEOF 0x04
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#define SG_PREFETCH_ADDR_MASK 0x03
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#define SG_PREFETCH_ALIGN_MASK 0x02
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#define SG_PREFETCH_CNT_LIMIT 0x01
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#define SG_PREFETCH_CNT 0x00
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#define DOWNLOAD_CONST_COUNT 0x08
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/* Exported Labels */
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#define LABEL_seq_isr 0x28f
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#define LABEL_timer_isr 0x28b
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