232 lines
5.9 KiB
C
232 lines
5.9 KiB
C
/*
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* This file is part of wl1251
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*
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* Copyright (c) 1998-2007 Texas Instruments Incorporated
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* Copyright (C) 2008 Nokia Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*
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*/
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#ifndef __WL1251_TX_H__
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#define __WL1251_TX_H__
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#include <linux/bitops.h>
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#include "acx.h"
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/*
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*
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* TX PATH
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*
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* The Tx path uses a double buffer and a tx_control structure, each located
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* at a fixed address in the device's memory. On startup, the host retrieves
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* the pointers to these addresses. A double buffer allows for continuous data
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* flow towards the device. The host keeps track of which buffer is available
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* and alternates between these two buffers on a per packet basis.
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*
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* The size of each of the two buffers is large enough to hold the longest
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* 802.3 packet - maximum size Ethernet packet + header + descriptor.
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* TX complete indication will be received a-synchronously in a TX done cyclic
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* buffer which is composed of 16 tx_result descriptors structures and is used
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* in a cyclic manner.
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*
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* The TX (HOST) procedure is as follows:
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* 1. Read the Tx path status, that will give the data_out_count.
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* 2. goto 1, if not possible.
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* i.e. if data_in_count - data_out_count >= HwBuffer size (2 for double
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* buffer).
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* 3. Copy the packet (preceded by double_buffer_desc), if possible.
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* i.e. if data_in_count - data_out_count < HwBuffer size (2 for double
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* buffer).
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* 4. increment data_in_count.
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* 5. Inform the firmware by generating a firmware internal interrupt.
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* 6. FW will increment data_out_count after it reads the buffer.
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*
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* The TX Complete procedure:
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* 1. To get a TX complete indication the host enables the tx_complete flag in
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* the TX descriptor Structure.
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* 2. For each packet with a Tx Complete field set, the firmware adds the
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* transmit results to the cyclic buffer (txDoneRing) and sets both done_1
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* and done_2 to 1 to indicate driver ownership.
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* 3. The firmware sends a Tx Complete interrupt to the host to trigger the
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* host to process the new data. Note: interrupt will be send per packet if
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* TX complete indication was requested in tx_control or per crossing
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* aggregation threshold.
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* 4. After receiving the Tx Complete interrupt, the host reads the
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* TxDescriptorDone information in a cyclic manner and clears both done_1
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* and done_2 fields.
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*
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*/
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#define TX_COMPLETE_REQUIRED_BIT 0x80
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#define TX_STATUS_DATA_OUT_COUNT_MASK 0xf
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#define WL1251_TX_ALIGN_TO 4
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#define WL1251_TX_ALIGN(len) (((len) + WL1251_TX_ALIGN_TO - 1) & \
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~(WL1251_TX_ALIGN_TO - 1))
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#define WL1251_TKIP_IV_SPACE 4
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struct tx_control {
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/* Rate Policy (class) index */
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unsigned rate_policy:3;
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/* When set, no ack policy is expected */
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unsigned ack_policy:1;
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/*
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* Packet type:
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* 0 -> 802.11
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* 1 -> 802.3
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* 2 -> IP
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* 3 -> raw codec
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*/
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unsigned packet_type:2;
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/* If set, this is a QoS-Null or QoS-Data frame */
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unsigned qos:1;
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/*
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* If set, the target triggers the tx complete INT
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* upon frame sending completion.
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*/
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unsigned tx_complete:1;
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/* 2 bytes padding before packet header */
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unsigned xfer_pad:1;
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unsigned reserved:7;
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} __packed;
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struct tx_double_buffer_desc {
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/* Length of payload, including headers. */
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__le16 length;
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/*
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* A bit mask that specifies the initial rate to be used
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* Possible values are:
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* 0x0001 - 1Mbits
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* 0x0002 - 2Mbits
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* 0x0004 - 5.5Mbits
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* 0x0008 - 6Mbits
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* 0x0010 - 9Mbits
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* 0x0020 - 11Mbits
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* 0x0040 - 12Mbits
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* 0x0080 - 18Mbits
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* 0x0100 - 22Mbits
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* 0x0200 - 24Mbits
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* 0x0400 - 36Mbits
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* 0x0800 - 48Mbits
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* 0x1000 - 54Mbits
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*/
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__le16 rate;
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/* Time in us that a packet can spend in the target */
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__le32 expiry_time;
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/* index of the TX queue used for this packet */
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u8 xmit_queue;
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/* Used to identify a packet */
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u8 id;
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struct tx_control control;
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/*
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* The FW should cut the packet into fragments
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* of this size.
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*/
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__le16 frag_threshold;
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/* Numbers of HW queue blocks to be allocated */
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u8 num_mem_blocks;
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u8 reserved;
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} __packed;
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enum {
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TX_SUCCESS = 0,
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TX_DMA_ERROR = BIT(7),
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TX_DISABLED = BIT(6),
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TX_RETRY_EXCEEDED = BIT(5),
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TX_TIMEOUT = BIT(4),
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TX_KEY_NOT_FOUND = BIT(3),
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TX_ENCRYPT_FAIL = BIT(2),
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TX_UNAVAILABLE_PRIORITY = BIT(1),
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};
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struct tx_result {
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/*
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* Ownership synchronization between the host and
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* the firmware. If done_1 and done_2 are cleared,
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* owned by the FW (no info ready).
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*/
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u8 done_1;
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/* same as double_buffer_desc->id */
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u8 id;
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/*
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* Total air access duration consumed by this
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* packet, including all retries and overheads.
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*/
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u16 medium_usage;
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/* Total media delay (from 1st EDCA AIFS counter until TX Complete). */
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u32 medium_delay;
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/* Time between host xfer and tx complete */
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u32 fw_hnadling_time;
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/* The LS-byte of the last TKIP sequence number. */
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u8 lsb_seq_num;
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/* Retry count */
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u8 ack_failures;
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/* At which rate we got a ACK */
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u16 rate;
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u16 reserved;
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/* TX_* */
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u8 status;
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/* See done_1 */
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u8 done_2;
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} __packed;
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static inline int wl1251_tx_get_queue(int queue)
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{
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switch (queue) {
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case 0:
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return QOS_AC_VO;
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case 1:
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return QOS_AC_VI;
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case 2:
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return QOS_AC_BE;
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case 3:
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return QOS_AC_BK;
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default:
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return QOS_AC_BE;
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}
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}
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void wl1251_tx_work(struct work_struct *work);
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void wl1251_tx_complete(struct wl1251 *wl);
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void wl1251_tx_flush(struct wl1251 *wl);
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#endif
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