268 lines
7.1 KiB
C
268 lines
7.1 KiB
C
/*******************************************************************************
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Copyright (C) 2007-2009 STMicroelectronics Ltd
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
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*******************************************************************************/
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#include <linux/io.h>
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#include "common.h"
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#include "dwmac_dma.h"
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#define GMAC_HI_REG_AE 0x80000000
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/* CSR1 enables the transmit DMA to check for new descriptor */
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void dwmac_enable_dma_transmission(void __iomem *ioaddr)
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{
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writel(1, ioaddr + DMA_XMT_POLL_DEMAND);
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}
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void dwmac_enable_dma_irq(void __iomem *ioaddr)
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{
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writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);
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}
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void dwmac_disable_dma_irq(void __iomem *ioaddr)
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{
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writel(0, ioaddr + DMA_INTR_ENA);
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}
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void dwmac_dma_start_tx(void __iomem *ioaddr)
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{
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u32 value = readl(ioaddr + DMA_CONTROL);
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value |= DMA_CONTROL_ST;
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writel(value, ioaddr + DMA_CONTROL);
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}
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void dwmac_dma_stop_tx(void __iomem *ioaddr)
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{
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u32 value = readl(ioaddr + DMA_CONTROL);
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value &= ~DMA_CONTROL_ST;
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writel(value, ioaddr + DMA_CONTROL);
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}
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void dwmac_dma_start_rx(void __iomem *ioaddr)
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{
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u32 value = readl(ioaddr + DMA_CONTROL);
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value |= DMA_CONTROL_SR;
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writel(value, ioaddr + DMA_CONTROL);
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}
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void dwmac_dma_stop_rx(void __iomem *ioaddr)
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{
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u32 value = readl(ioaddr + DMA_CONTROL);
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value &= ~DMA_CONTROL_SR;
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writel(value, ioaddr + DMA_CONTROL);
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}
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#ifdef DWMAC_DMA_DEBUG
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static void show_tx_process_state(unsigned int status)
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{
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unsigned int state;
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state = (status & DMA_STATUS_TS_MASK) >> DMA_STATUS_TS_SHIFT;
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switch (state) {
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case 0:
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pr_debug("- TX (Stopped): Reset or Stop command\n");
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break;
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case 1:
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pr_debug("- TX (Running):Fetching the Tx desc\n");
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break;
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case 2:
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pr_debug("- TX (Running): Waiting for end of tx\n");
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break;
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case 3:
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pr_debug("- TX (Running): Reading the data "
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"and queuing the data into the Tx buf\n");
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break;
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case 6:
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pr_debug("- TX (Suspended): Tx Buff Underflow "
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"or an unavailable Transmit descriptor\n");
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break;
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case 7:
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pr_debug("- TX (Running): Closing Tx descriptor\n");
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break;
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default:
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break;
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}
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}
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static void show_rx_process_state(unsigned int status)
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{
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unsigned int state;
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state = (status & DMA_STATUS_RS_MASK) >> DMA_STATUS_RS_SHIFT;
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switch (state) {
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case 0:
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pr_debug("- RX (Stopped): Reset or Stop command\n");
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break;
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case 1:
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pr_debug("- RX (Running): Fetching the Rx desc\n");
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break;
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case 2:
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pr_debug("- RX (Running):Checking for end of pkt\n");
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break;
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case 3:
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pr_debug("- RX (Running): Waiting for Rx pkt\n");
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break;
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case 4:
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pr_debug("- RX (Suspended): Unavailable Rx buf\n");
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break;
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case 5:
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pr_debug("- RX (Running): Closing Rx descriptor\n");
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break;
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case 6:
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pr_debug("- RX(Running): Flushing the current frame"
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" from the Rx buf\n");
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break;
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case 7:
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pr_debug("- RX (Running): Queuing the Rx frame"
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" from the Rx buf into memory\n");
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break;
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default:
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break;
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}
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}
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#endif
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int dwmac_dma_interrupt(void __iomem *ioaddr,
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struct stmmac_extra_stats *x)
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{
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int ret = 0;
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/* read the status register (CSR5) */
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u32 intr_status = readl(ioaddr + DMA_STATUS);
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#ifdef DWMAC_DMA_DEBUG
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/* Enable it to monitor DMA rx/tx status in case of critical problems */
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pr_debug("%s: [CSR5: 0x%08x]\n", __func__, intr_status);
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show_tx_process_state(intr_status);
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show_rx_process_state(intr_status);
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#endif
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/* ABNORMAL interrupts */
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if (unlikely(intr_status & DMA_STATUS_AIS)) {
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if (unlikely(intr_status & DMA_STATUS_UNF)) {
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ret = tx_hard_error_bump_tc;
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x->tx_undeflow_irq++;
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}
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if (unlikely(intr_status & DMA_STATUS_TJT))
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x->tx_jabber_irq++;
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if (unlikely(intr_status & DMA_STATUS_OVF))
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x->rx_overflow_irq++;
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if (unlikely(intr_status & DMA_STATUS_RU))
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x->rx_buf_unav_irq++;
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if (unlikely(intr_status & DMA_STATUS_RPS))
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x->rx_process_stopped_irq++;
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if (unlikely(intr_status & DMA_STATUS_RWT))
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x->rx_watchdog_irq++;
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if (unlikely(intr_status & DMA_STATUS_ETI))
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x->tx_early_irq++;
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if (unlikely(intr_status & DMA_STATUS_TPS)) {
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x->tx_process_stopped_irq++;
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ret = tx_hard_error;
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}
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if (unlikely(intr_status & DMA_STATUS_FBI)) {
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x->fatal_bus_error_irq++;
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ret = tx_hard_error;
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}
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}
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/* TX/RX NORMAL interrupts */
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if (likely(intr_status & DMA_STATUS_NIS)) {
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x->normal_irq_n++;
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if (likely(intr_status & DMA_STATUS_RI)) {
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u32 value = readl(ioaddr + DMA_INTR_ENA);
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/* to schedule NAPI on real RIE event. */
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if (likely(value & DMA_INTR_ENA_RIE)) {
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x->rx_normal_irq_n++;
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ret |= handle_rx;
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}
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}
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if (likely(intr_status & DMA_STATUS_TI)) {
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x->tx_normal_irq_n++;
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ret |= handle_tx;
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}
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if (unlikely(intr_status & DMA_STATUS_ERI))
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x->rx_early_irq++;
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}
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/* Optional hardware blocks, interrupts should be disabled */
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if (unlikely(intr_status &
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(DMA_STATUS_GPI | DMA_STATUS_GMI | DMA_STATUS_GLI)))
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pr_warn("%s: unexpected status %08x\n", __func__, intr_status);
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/* Clear the interrupt by writing a logic 1 to the CSR5[15-0] */
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writel((intr_status & 0x1ffff), ioaddr + DMA_STATUS);
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return ret;
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}
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void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr)
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{
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u32 csr6 = readl(ioaddr + DMA_CONTROL);
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writel((csr6 | DMA_CONTROL_FTF), ioaddr + DMA_CONTROL);
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do {} while ((readl(ioaddr + DMA_CONTROL) & DMA_CONTROL_FTF));
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}
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void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
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unsigned int high, unsigned int low)
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{
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unsigned long data;
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data = (addr[5] << 8) | addr[4];
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/* For MAC Addr registers se have to set the Address Enable (AE)
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* bit that has no effect on the High Reg 0 where the bit 31 (MO)
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* is RO.
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*/
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writel(data | GMAC_HI_REG_AE, ioaddr + high);
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data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
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writel(data, ioaddr + low);
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}
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/* Enable disable MAC RX/TX */
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void stmmac_set_mac(void __iomem *ioaddr, bool enable)
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{
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u32 value = readl(ioaddr + MAC_CTRL_REG);
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if (enable)
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value |= MAC_RNABLE_RX | MAC_ENABLE_TX;
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else
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value &= ~(MAC_ENABLE_TX | MAC_RNABLE_RX);
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writel(value, ioaddr + MAC_CTRL_REG);
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}
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void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
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unsigned int high, unsigned int low)
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{
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unsigned int hi_addr, lo_addr;
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/* Read the MAC address from the hardware */
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hi_addr = readl(ioaddr + high);
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lo_addr = readl(ioaddr + low);
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/* Extract the MAC address from the high and low words */
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addr[0] = lo_addr & 0xff;
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addr[1] = (lo_addr >> 8) & 0xff;
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addr[2] = (lo_addr >> 16) & 0xff;
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addr[3] = (lo_addr >> 24) & 0xff;
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addr[4] = hi_addr & 0xff;
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addr[5] = (hi_addr >> 8) & 0xff;
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}
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