387 lines
10 KiB
C
387 lines
10 KiB
C
/*
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* Copyright (c) 2014 MundoReader S.L.
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* Author: Heiko Stuebner <heiko@sntech.de>
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*
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* based on
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*
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* samsung/clk.h
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* Copyright (c) 2013 Samsung Electronics Co., Ltd.
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* Copyright (c) 2013 Linaro Ltd.
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* Author: Thomas Abraham <thomas.ab@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef CLK_ROCKCHIP_CLK_H
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#define CLK_ROCKCHIP_CLK_H
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#define HIWORD_UPDATE(val, mask, shift) \
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((val) << (shift) | (mask) << ((shift) + 16))
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/* register positions shared by RK2928, RK3066 and RK3188 */
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#define RK2928_PLL_CON(x) (x * 0x4)
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#define RK2928_MODE_CON 0x40
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#define RK2928_CLKSEL_CON(x) (x * 0x4 + 0x44)
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#define RK2928_CLKGATE_CON(x) (x * 0x4 + 0xd0)
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#define RK2928_GLB_SRST_FST 0x100
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#define RK2928_GLB_SRST_SND 0x104
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#define RK2928_SOFTRST_CON(x) (x * 0x4 + 0x110)
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#define RK2928_MISC_CON 0x134
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#define RK3288_PLL_CON(x) RK2928_PLL_CON(x)
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#define RK3288_MODE_CON 0x50
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#define RK3288_CLKSEL_CON(x) (x * 0x4 + 0x60)
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#define RK3288_CLKGATE_CON(x) (x * 0x4 + 0x160)
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#define RK3288_GLB_SRST_FST 0x1b0
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#define RK3288_GLB_SRST_SND 0x1b4
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#define RK3288_SOFTRST_CON(x) (x * 0x4 + 0x1b8)
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#define RK3288_MISC_CON 0x1e8
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enum rockchip_pll_type {
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pll_rk3066,
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};
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#define RK3066_PLL_RATE(_rate, _nr, _nf, _no) \
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{ \
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.rate = _rate##U, \
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.nr = _nr, \
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.nf = _nf, \
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.no = _no, \
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.bwadj = (_nf >> 1), \
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}
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struct rockchip_pll_rate_table {
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unsigned long rate;
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unsigned int nr;
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unsigned int nf;
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unsigned int no;
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unsigned int bwadj;
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};
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/**
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* struct rockchip_pll_clock: information about pll clock
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* @id: platform specific id of the clock.
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* @name: name of this pll clock.
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* @parent_name: name of the parent clock.
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* @flags: optional flags for basic clock.
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* @con_offset: offset of the register for configuring the PLL.
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* @mode_offset: offset of the register for configuring the PLL-mode.
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* @mode_shift: offset inside the mode-register for the mode of this pll.
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* @lock_shift: offset inside the lock register for the lock status.
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* @type: Type of PLL to be registered.
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* @rate_table: Table of usable pll rates
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*/
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struct rockchip_pll_clock {
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unsigned int id;
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const char *name;
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const char **parent_names;
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u8 num_parents;
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unsigned long flags;
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int con_offset;
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int mode_offset;
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int mode_shift;
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int lock_shift;
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enum rockchip_pll_type type;
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struct rockchip_pll_rate_table *rate_table;
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};
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#define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \
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_lshift, _rtable) \
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{ \
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.id = _id, \
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.type = _type, \
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.name = _name, \
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.parent_names = _pnames, \
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.num_parents = ARRAY_SIZE(_pnames), \
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.flags = CLK_GET_RATE_NOCACHE | _flags, \
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.con_offset = _con, \
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.mode_offset = _mode, \
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.mode_shift = _mshift, \
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.lock_shift = _lshift, \
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.rate_table = _rtable, \
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}
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struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type,
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const char *name, const char **parent_names, u8 num_parents,
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void __iomem *base, int con_offset, int grf_lock_offset,
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int lock_shift, int reg_mode, int mode_shift,
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struct rockchip_pll_rate_table *rate_table,
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spinlock_t *lock);
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struct rockchip_cpuclk_clksel {
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int reg;
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u32 val;
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};
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#define ROCKCHIP_CPUCLK_NUM_DIVIDERS 2
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struct rockchip_cpuclk_rate_table {
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unsigned long prate;
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struct rockchip_cpuclk_clksel divs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
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};
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/**
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* struct rockchip_cpuclk_reg_data: describes register offsets and masks of the cpuclock
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* @core_reg: register offset of the core settings register
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* @div_core_shift: core divider offset used to divide the pll value
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* @div_core_mask: core divider mask
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* @mux_core_shift: offset of the core multiplexer
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*/
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struct rockchip_cpuclk_reg_data {
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int core_reg;
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u8 div_core_shift;
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u32 div_core_mask;
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int mux_core_reg;
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u8 mux_core_shift;
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};
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struct clk *rockchip_clk_register_cpuclk(const char *name,
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const char **parent_names, u8 num_parents,
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const struct rockchip_cpuclk_reg_data *reg_data,
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const struct rockchip_cpuclk_rate_table *rates,
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int nrates, void __iomem *reg_base, spinlock_t *lock);
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#define PNAME(x) static const char *x[] __initconst
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enum rockchip_clk_branch_type {
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branch_composite,
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branch_mux,
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branch_divider,
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branch_fraction_divider,
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branch_gate,
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};
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struct rockchip_clk_branch {
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unsigned int id;
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enum rockchip_clk_branch_type branch_type;
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const char *name;
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const char **parent_names;
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u8 num_parents;
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unsigned long flags;
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int muxdiv_offset;
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u8 mux_shift;
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u8 mux_width;
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u8 mux_flags;
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u8 div_shift;
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u8 div_width;
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u8 div_flags;
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struct clk_div_table *div_table;
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int gate_offset;
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u8 gate_shift;
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u8 gate_flags;
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};
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#define COMPOSITE(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\
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df, go, gs, gf) \
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{ \
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.id = _id, \
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.branch_type = branch_composite, \
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.name = cname, \
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.parent_names = pnames, \
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.num_parents = ARRAY_SIZE(pnames), \
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.flags = f, \
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.muxdiv_offset = mo, \
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.mux_shift = ms, \
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.mux_width = mw, \
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.mux_flags = mf, \
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.div_shift = ds, \
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.div_width = dw, \
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.div_flags = df, \
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.gate_offset = go, \
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.gate_shift = gs, \
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.gate_flags = gf, \
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}
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#define COMPOSITE_NOMUX(_id, cname, pname, f, mo, ds, dw, df, \
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go, gs, gf) \
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{ \
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.id = _id, \
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.branch_type = branch_composite, \
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.name = cname, \
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.parent_names = (const char *[]){ pname }, \
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.num_parents = 1, \
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.flags = f, \
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.muxdiv_offset = mo, \
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.div_shift = ds, \
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.div_width = dw, \
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.div_flags = df, \
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.gate_offset = go, \
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.gate_shift = gs, \
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.gate_flags = gf, \
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}
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#define COMPOSITE_NOMUX_DIVTBL(_id, cname, pname, f, mo, ds, dw,\
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df, dt, go, gs, gf) \
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{ \
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.id = _id, \
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.branch_type = branch_composite, \
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.name = cname, \
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.parent_names = (const char *[]){ pname }, \
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.num_parents = 1, \
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.flags = f, \
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.muxdiv_offset = mo, \
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.div_shift = ds, \
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.div_width = dw, \
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.div_flags = df, \
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.div_table = dt, \
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.gate_offset = go, \
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.gate_shift = gs, \
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.gate_flags = gf, \
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}
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#define COMPOSITE_NODIV(_id, cname, pnames, f, mo, ms, mw, mf, \
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go, gs, gf) \
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{ \
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.id = _id, \
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.branch_type = branch_composite, \
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.name = cname, \
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.parent_names = pnames, \
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.num_parents = ARRAY_SIZE(pnames), \
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.flags = f, \
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.muxdiv_offset = mo, \
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.mux_shift = ms, \
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.mux_width = mw, \
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.mux_flags = mf, \
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.gate_offset = go, \
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.gate_shift = gs, \
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.gate_flags = gf, \
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}
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#define COMPOSITE_NOGATE(_id, cname, pnames, f, mo, ms, mw, mf, \
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ds, dw, df) \
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{ \
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.id = _id, \
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.branch_type = branch_composite, \
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.name = cname, \
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.parent_names = pnames, \
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.num_parents = ARRAY_SIZE(pnames), \
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.flags = f, \
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.muxdiv_offset = mo, \
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.mux_shift = ms, \
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.mux_width = mw, \
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.mux_flags = mf, \
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.div_shift = ds, \
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.div_width = dw, \
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.div_flags = df, \
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.gate_offset = -1, \
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}
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#define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf)\
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{ \
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.id = _id, \
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.branch_type = branch_fraction_divider, \
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.name = cname, \
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.parent_names = (const char *[]){ pname }, \
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.num_parents = 1, \
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.flags = f, \
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.muxdiv_offset = mo, \
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.div_shift = 16, \
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.div_width = 16, \
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.div_flags = df, \
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.gate_offset = go, \
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.gate_shift = gs, \
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.gate_flags = gf, \
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}
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#define MUX(_id, cname, pnames, f, o, s, w, mf) \
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{ \
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.id = _id, \
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.branch_type = branch_mux, \
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.name = cname, \
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.parent_names = pnames, \
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.num_parents = ARRAY_SIZE(pnames), \
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.flags = f, \
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.muxdiv_offset = o, \
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.mux_shift = s, \
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.mux_width = w, \
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.mux_flags = mf, \
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.gate_offset = -1, \
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}
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#define DIV(_id, cname, pname, f, o, s, w, df) \
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{ \
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.id = _id, \
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.branch_type = branch_divider, \
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.name = cname, \
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.parent_names = (const char *[]){ pname }, \
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.num_parents = 1, \
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.flags = f, \
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.muxdiv_offset = o, \
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.div_shift = s, \
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.div_width = w, \
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.div_flags = df, \
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.gate_offset = -1, \
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}
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#define DIVTBL(_id, cname, pname, f, o, s, w, df, dt) \
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{ \
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.id = _id, \
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.branch_type = branch_divider, \
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.name = cname, \
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.parent_names = (const char *[]){ pname }, \
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.num_parents = 1, \
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.flags = f, \
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.muxdiv_offset = o, \
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.div_shift = s, \
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.div_width = w, \
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.div_flags = df, \
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.div_table = dt, \
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}
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#define GATE(_id, cname, pname, f, o, b, gf) \
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{ \
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.id = _id, \
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.branch_type = branch_gate, \
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.name = cname, \
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.parent_names = (const char *[]){ pname }, \
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.num_parents = 1, \
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.flags = f, \
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.gate_offset = o, \
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.gate_shift = b, \
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.gate_flags = gf, \
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}
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void rockchip_clk_init(struct device_node *np, void __iomem *base,
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unsigned long nr_clks);
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struct regmap *rockchip_clk_get_grf(void);
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void rockchip_clk_add_lookup(struct clk *clk, unsigned int id);
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void rockchip_clk_register_branches(struct rockchip_clk_branch *clk_list,
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unsigned int nr_clk);
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void rockchip_clk_register_plls(struct rockchip_pll_clock *pll_list,
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unsigned int nr_pll, int grf_lock_offset);
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void rockchip_clk_register_armclk(unsigned int lookup_id, const char *name,
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const char **parent_names, u8 num_parents,
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const struct rockchip_cpuclk_reg_data *reg_data,
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const struct rockchip_cpuclk_rate_table *rates,
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int nrates);
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void rockchip_clk_protect_critical(const char *clocks[], int nclocks);
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void rockchip_register_restart_notifier(unsigned int reg);
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#define ROCKCHIP_SOFTRST_HIWORD_MASK BIT(0)
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#ifdef CONFIG_RESET_CONTROLLER
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void rockchip_register_softrst(struct device_node *np,
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unsigned int num_regs,
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void __iomem *base, u8 flags);
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#else
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static inline void rockchip_register_softrst(struct device_node *np,
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unsigned int num_regs,
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void __iomem *base, u8 flags)
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{
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}
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#endif
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#endif
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