1280 lines
31 KiB
C
1280 lines
31 KiB
C
/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*
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* Copyright Novell Inc 2010
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*
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* Authors: Alexander Graf <agraf@suse.de>
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*/
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#include <asm/kvm.h>
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#include <asm/kvm_ppc.h>
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#include <asm/disassemble.h>
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#include <asm/kvm_book3s.h>
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#include <asm/kvm_fpu.h>
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#include <asm/reg.h>
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#include <asm/cacheflush.h>
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#include <asm/switch_to.h>
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#include <linux/vmalloc.h>
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/* #define DEBUG */
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#ifdef DEBUG
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#define dprintk printk
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#else
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#define dprintk(...) do { } while(0);
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#endif
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#define OP_LFS 48
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#define OP_LFSU 49
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#define OP_LFD 50
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#define OP_LFDU 51
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#define OP_STFS 52
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#define OP_STFSU 53
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#define OP_STFD 54
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#define OP_STFDU 55
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#define OP_PSQ_L 56
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#define OP_PSQ_LU 57
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#define OP_PSQ_ST 60
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#define OP_PSQ_STU 61
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#define OP_31_LFSX 535
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#define OP_31_LFSUX 567
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#define OP_31_LFDX 599
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#define OP_31_LFDUX 631
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#define OP_31_STFSX 663
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#define OP_31_STFSUX 695
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#define OP_31_STFX 727
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#define OP_31_STFUX 759
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#define OP_31_LWIZX 887
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#define OP_31_STFIWX 983
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#define OP_59_FADDS 21
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#define OP_59_FSUBS 20
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#define OP_59_FSQRTS 22
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#define OP_59_FDIVS 18
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#define OP_59_FRES 24
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#define OP_59_FMULS 25
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#define OP_59_FRSQRTES 26
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#define OP_59_FMSUBS 28
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#define OP_59_FMADDS 29
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#define OP_59_FNMSUBS 30
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#define OP_59_FNMADDS 31
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#define OP_63_FCMPU 0
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#define OP_63_FCPSGN 8
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#define OP_63_FRSP 12
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#define OP_63_FCTIW 14
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#define OP_63_FCTIWZ 15
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#define OP_63_FDIV 18
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#define OP_63_FADD 21
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#define OP_63_FSQRT 22
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#define OP_63_FSEL 23
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#define OP_63_FRE 24
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#define OP_63_FMUL 25
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#define OP_63_FRSQRTE 26
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#define OP_63_FMSUB 28
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#define OP_63_FMADD 29
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#define OP_63_FNMSUB 30
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#define OP_63_FNMADD 31
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#define OP_63_FCMPO 32
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#define OP_63_MTFSB1 38 // XXX
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#define OP_63_FSUB 20
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#define OP_63_FNEG 40
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#define OP_63_MCRFS 64
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#define OP_63_MTFSB0 70
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#define OP_63_FMR 72
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#define OP_63_MTFSFI 134
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#define OP_63_FABS 264
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#define OP_63_MFFS 583
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#define OP_63_MTFSF 711
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#define OP_4X_PS_CMPU0 0
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#define OP_4X_PSQ_LX 6
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#define OP_4XW_PSQ_STX 7
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#define OP_4A_PS_SUM0 10
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#define OP_4A_PS_SUM1 11
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#define OP_4A_PS_MULS0 12
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#define OP_4A_PS_MULS1 13
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#define OP_4A_PS_MADDS0 14
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#define OP_4A_PS_MADDS1 15
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#define OP_4A_PS_DIV 18
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#define OP_4A_PS_SUB 20
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#define OP_4A_PS_ADD 21
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#define OP_4A_PS_SEL 23
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#define OP_4A_PS_RES 24
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#define OP_4A_PS_MUL 25
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#define OP_4A_PS_RSQRTE 26
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#define OP_4A_PS_MSUB 28
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#define OP_4A_PS_MADD 29
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#define OP_4A_PS_NMSUB 30
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#define OP_4A_PS_NMADD 31
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#define OP_4X_PS_CMPO0 32
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#define OP_4X_PSQ_LUX 38
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#define OP_4XW_PSQ_STUX 39
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#define OP_4X_PS_NEG 40
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#define OP_4X_PS_CMPU1 64
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#define OP_4X_PS_MR 72
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#define OP_4X_PS_CMPO1 96
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#define OP_4X_PS_NABS 136
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#define OP_4X_PS_ABS 264
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#define OP_4X_PS_MERGE00 528
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#define OP_4X_PS_MERGE01 560
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#define OP_4X_PS_MERGE10 592
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#define OP_4X_PS_MERGE11 624
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#define SCALAR_NONE 0
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#define SCALAR_HIGH (1 << 0)
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#define SCALAR_LOW (1 << 1)
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#define SCALAR_NO_PS0 (1 << 2)
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#define SCALAR_NO_PS1 (1 << 3)
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#define GQR_ST_TYPE_MASK 0x00000007
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#define GQR_ST_TYPE_SHIFT 0
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#define GQR_ST_SCALE_MASK 0x00003f00
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#define GQR_ST_SCALE_SHIFT 8
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#define GQR_LD_TYPE_MASK 0x00070000
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#define GQR_LD_TYPE_SHIFT 16
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#define GQR_LD_SCALE_MASK 0x3f000000
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#define GQR_LD_SCALE_SHIFT 24
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#define GQR_QUANTIZE_FLOAT 0
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#define GQR_QUANTIZE_U8 4
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#define GQR_QUANTIZE_U16 5
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#define GQR_QUANTIZE_S8 6
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#define GQR_QUANTIZE_S16 7
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#define FPU_LS_SINGLE 0
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#define FPU_LS_DOUBLE 1
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#define FPU_LS_SINGLE_LOW 2
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static inline void kvmppc_sync_qpr(struct kvm_vcpu *vcpu, int rt)
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{
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kvm_cvt_df(&VCPU_FPR(vcpu, rt), &vcpu->arch.qpr[rt]);
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}
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static void kvmppc_inject_pf(struct kvm_vcpu *vcpu, ulong eaddr, bool is_store)
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{
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u32 dsisr;
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u64 msr = kvmppc_get_msr(vcpu);
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msr = kvmppc_set_field(msr, 33, 36, 0);
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msr = kvmppc_set_field(msr, 42, 47, 0);
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kvmppc_set_msr(vcpu, msr);
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kvmppc_set_dar(vcpu, eaddr);
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/* Page Fault */
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dsisr = kvmppc_set_field(0, 33, 33, 1);
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if (is_store)
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dsisr = kvmppc_set_field(dsisr, 38, 38, 1);
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kvmppc_set_dsisr(vcpu, dsisr);
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kvmppc_book3s_queue_irqprio(vcpu, BOOK3S_INTERRUPT_DATA_STORAGE);
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}
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static int kvmppc_emulate_fpr_load(struct kvm_run *run, struct kvm_vcpu *vcpu,
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int rs, ulong addr, int ls_type)
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{
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int emulated = EMULATE_FAIL;
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int r;
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char tmp[8];
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int len = sizeof(u32);
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if (ls_type == FPU_LS_DOUBLE)
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len = sizeof(u64);
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/* read from memory */
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r = kvmppc_ld(vcpu, &addr, len, tmp, true);
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vcpu->arch.paddr_accessed = addr;
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if (r < 0) {
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kvmppc_inject_pf(vcpu, addr, false);
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goto done_load;
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} else if (r == EMULATE_DO_MMIO) {
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emulated = kvmppc_handle_load(run, vcpu, KVM_MMIO_REG_FPR | rs,
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len, 1);
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goto done_load;
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}
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emulated = EMULATE_DONE;
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/* put in registers */
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switch (ls_type) {
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case FPU_LS_SINGLE:
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kvm_cvt_fd((u32*)tmp, &VCPU_FPR(vcpu, rs));
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vcpu->arch.qpr[rs] = *((u32*)tmp);
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break;
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case FPU_LS_DOUBLE:
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VCPU_FPR(vcpu, rs) = *((u64*)tmp);
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break;
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}
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dprintk(KERN_INFO "KVM: FPR_LD [0x%llx] at 0x%lx (%d)\n", *(u64*)tmp,
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addr, len);
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done_load:
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return emulated;
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}
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static int kvmppc_emulate_fpr_store(struct kvm_run *run, struct kvm_vcpu *vcpu,
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int rs, ulong addr, int ls_type)
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{
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int emulated = EMULATE_FAIL;
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int r;
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char tmp[8];
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u64 val;
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int len;
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switch (ls_type) {
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case FPU_LS_SINGLE:
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kvm_cvt_df(&VCPU_FPR(vcpu, rs), (u32*)tmp);
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val = *((u32*)tmp);
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len = sizeof(u32);
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break;
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case FPU_LS_SINGLE_LOW:
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*((u32*)tmp) = VCPU_FPR(vcpu, rs);
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val = VCPU_FPR(vcpu, rs) & 0xffffffff;
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len = sizeof(u32);
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break;
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case FPU_LS_DOUBLE:
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*((u64*)tmp) = VCPU_FPR(vcpu, rs);
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val = VCPU_FPR(vcpu, rs);
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len = sizeof(u64);
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break;
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default:
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val = 0;
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len = 0;
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}
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r = kvmppc_st(vcpu, &addr, len, tmp, true);
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vcpu->arch.paddr_accessed = addr;
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if (r < 0) {
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kvmppc_inject_pf(vcpu, addr, true);
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} else if (r == EMULATE_DO_MMIO) {
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emulated = kvmppc_handle_store(run, vcpu, val, len, 1);
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} else {
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emulated = EMULATE_DONE;
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}
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dprintk(KERN_INFO "KVM: FPR_ST [0x%llx] at 0x%lx (%d)\n",
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val, addr, len);
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return emulated;
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}
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static int kvmppc_emulate_psq_load(struct kvm_run *run, struct kvm_vcpu *vcpu,
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int rs, ulong addr, bool w, int i)
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{
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int emulated = EMULATE_FAIL;
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int r;
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float one = 1.0;
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u32 tmp[2];
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/* read from memory */
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if (w) {
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r = kvmppc_ld(vcpu, &addr, sizeof(u32), tmp, true);
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memcpy(&tmp[1], &one, sizeof(u32));
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} else {
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r = kvmppc_ld(vcpu, &addr, sizeof(u32) * 2, tmp, true);
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}
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vcpu->arch.paddr_accessed = addr;
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if (r < 0) {
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kvmppc_inject_pf(vcpu, addr, false);
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goto done_load;
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} else if ((r == EMULATE_DO_MMIO) && w) {
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emulated = kvmppc_handle_load(run, vcpu, KVM_MMIO_REG_FPR | rs,
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4, 1);
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vcpu->arch.qpr[rs] = tmp[1];
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goto done_load;
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} else if (r == EMULATE_DO_MMIO) {
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emulated = kvmppc_handle_load(run, vcpu, KVM_MMIO_REG_FQPR | rs,
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8, 1);
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goto done_load;
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}
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emulated = EMULATE_DONE;
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/* put in registers */
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kvm_cvt_fd(&tmp[0], &VCPU_FPR(vcpu, rs));
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vcpu->arch.qpr[rs] = tmp[1];
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dprintk(KERN_INFO "KVM: PSQ_LD [0x%x, 0x%x] at 0x%lx (%d)\n", tmp[0],
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tmp[1], addr, w ? 4 : 8);
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done_load:
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return emulated;
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}
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static int kvmppc_emulate_psq_store(struct kvm_run *run, struct kvm_vcpu *vcpu,
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int rs, ulong addr, bool w, int i)
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{
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int emulated = EMULATE_FAIL;
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int r;
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u32 tmp[2];
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int len = w ? sizeof(u32) : sizeof(u64);
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kvm_cvt_df(&VCPU_FPR(vcpu, rs), &tmp[0]);
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tmp[1] = vcpu->arch.qpr[rs];
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r = kvmppc_st(vcpu, &addr, len, tmp, true);
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vcpu->arch.paddr_accessed = addr;
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if (r < 0) {
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kvmppc_inject_pf(vcpu, addr, true);
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} else if ((r == EMULATE_DO_MMIO) && w) {
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emulated = kvmppc_handle_store(run, vcpu, tmp[0], 4, 1);
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} else if (r == EMULATE_DO_MMIO) {
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u64 val = ((u64)tmp[0] << 32) | tmp[1];
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emulated = kvmppc_handle_store(run, vcpu, val, 8, 1);
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} else {
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emulated = EMULATE_DONE;
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}
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dprintk(KERN_INFO "KVM: PSQ_ST [0x%x, 0x%x] at 0x%lx (%d)\n",
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tmp[0], tmp[1], addr, len);
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return emulated;
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}
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/*
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* Cuts out inst bits with ordering according to spec.
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* That means the leftmost bit is zero. All given bits are included.
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*/
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static inline u32 inst_get_field(u32 inst, int msb, int lsb)
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{
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return kvmppc_get_field(inst, msb + 32, lsb + 32);
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}
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/*
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* Replaces inst bits with ordering according to spec.
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*/
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static inline u32 inst_set_field(u32 inst, int msb, int lsb, int value)
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{
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return kvmppc_set_field(inst, msb + 32, lsb + 32, value);
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}
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bool kvmppc_inst_is_paired_single(struct kvm_vcpu *vcpu, u32 inst)
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{
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if (!(vcpu->arch.hflags & BOOK3S_HFLAG_PAIRED_SINGLE))
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return false;
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switch (get_op(inst)) {
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case OP_PSQ_L:
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case OP_PSQ_LU:
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case OP_PSQ_ST:
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case OP_PSQ_STU:
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case OP_LFS:
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case OP_LFSU:
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case OP_LFD:
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case OP_LFDU:
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case OP_STFS:
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case OP_STFSU:
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case OP_STFD:
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case OP_STFDU:
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return true;
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case 4:
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/* X form */
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switch (inst_get_field(inst, 21, 30)) {
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case OP_4X_PS_CMPU0:
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case OP_4X_PSQ_LX:
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case OP_4X_PS_CMPO0:
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case OP_4X_PSQ_LUX:
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case OP_4X_PS_NEG:
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case OP_4X_PS_CMPU1:
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case OP_4X_PS_MR:
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case OP_4X_PS_CMPO1:
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case OP_4X_PS_NABS:
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case OP_4X_PS_ABS:
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case OP_4X_PS_MERGE00:
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case OP_4X_PS_MERGE01:
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case OP_4X_PS_MERGE10:
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case OP_4X_PS_MERGE11:
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return true;
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}
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/* XW form */
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switch (inst_get_field(inst, 25, 30)) {
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case OP_4XW_PSQ_STX:
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case OP_4XW_PSQ_STUX:
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return true;
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}
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/* A form */
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switch (inst_get_field(inst, 26, 30)) {
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case OP_4A_PS_SUM1:
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case OP_4A_PS_SUM0:
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case OP_4A_PS_MULS0:
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case OP_4A_PS_MULS1:
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case OP_4A_PS_MADDS0:
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case OP_4A_PS_MADDS1:
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case OP_4A_PS_DIV:
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case OP_4A_PS_SUB:
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case OP_4A_PS_ADD:
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case OP_4A_PS_SEL:
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case OP_4A_PS_RES:
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case OP_4A_PS_MUL:
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case OP_4A_PS_RSQRTE:
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case OP_4A_PS_MSUB:
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case OP_4A_PS_MADD:
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case OP_4A_PS_NMSUB:
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case OP_4A_PS_NMADD:
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return true;
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}
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break;
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case 59:
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switch (inst_get_field(inst, 21, 30)) {
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case OP_59_FADDS:
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case OP_59_FSUBS:
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case OP_59_FDIVS:
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case OP_59_FRES:
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case OP_59_FRSQRTES:
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return true;
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}
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switch (inst_get_field(inst, 26, 30)) {
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case OP_59_FMULS:
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case OP_59_FMSUBS:
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case OP_59_FMADDS:
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case OP_59_FNMSUBS:
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case OP_59_FNMADDS:
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return true;
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}
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break;
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case 63:
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switch (inst_get_field(inst, 21, 30)) {
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case OP_63_MTFSB0:
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case OP_63_MTFSB1:
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case OP_63_MTFSF:
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case OP_63_MTFSFI:
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case OP_63_MCRFS:
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case OP_63_MFFS:
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case OP_63_FCMPU:
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case OP_63_FCMPO:
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case OP_63_FNEG:
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case OP_63_FMR:
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case OP_63_FABS:
|
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case OP_63_FRSP:
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case OP_63_FDIV:
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case OP_63_FADD:
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case OP_63_FSUB:
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case OP_63_FCTIW:
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case OP_63_FCTIWZ:
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case OP_63_FRSQRTE:
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case OP_63_FCPSGN:
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return true;
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|
}
|
|
switch (inst_get_field(inst, 26, 30)) {
|
|
case OP_63_FMUL:
|
|
case OP_63_FSEL:
|
|
case OP_63_FMSUB:
|
|
case OP_63_FMADD:
|
|
case OP_63_FNMSUB:
|
|
case OP_63_FNMADD:
|
|
return true;
|
|
}
|
|
break;
|
|
case 31:
|
|
switch (inst_get_field(inst, 21, 30)) {
|
|
case OP_31_LFSX:
|
|
case OP_31_LFSUX:
|
|
case OP_31_LFDX:
|
|
case OP_31_LFDUX:
|
|
case OP_31_STFSX:
|
|
case OP_31_STFSUX:
|
|
case OP_31_STFX:
|
|
case OP_31_STFUX:
|
|
case OP_31_STFIWX:
|
|
return true;
|
|
}
|
|
break;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
static int get_d_signext(u32 inst)
|
|
{
|
|
int d = inst & 0x8ff;
|
|
|
|
if (d & 0x800)
|
|
return -(d & 0x7ff);
|
|
|
|
return (d & 0x7ff);
|
|
}
|
|
|
|
static int kvmppc_ps_three_in(struct kvm_vcpu *vcpu, bool rc,
|
|
int reg_out, int reg_in1, int reg_in2,
|
|
int reg_in3, int scalar,
|
|
void (*func)(u64 *fpscr,
|
|
u32 *dst, u32 *src1,
|
|
u32 *src2, u32 *src3))
|
|
{
|
|
u32 *qpr = vcpu->arch.qpr;
|
|
u32 ps0_out;
|
|
u32 ps0_in1, ps0_in2, ps0_in3;
|
|
u32 ps1_in1, ps1_in2, ps1_in3;
|
|
|
|
/* RC */
|
|
WARN_ON(rc);
|
|
|
|
/* PS0 */
|
|
kvm_cvt_df(&VCPU_FPR(vcpu, reg_in1), &ps0_in1);
|
|
kvm_cvt_df(&VCPU_FPR(vcpu, reg_in2), &ps0_in2);
|
|
kvm_cvt_df(&VCPU_FPR(vcpu, reg_in3), &ps0_in3);
|
|
|
|
if (scalar & SCALAR_LOW)
|
|
ps0_in2 = qpr[reg_in2];
|
|
|
|
func(&vcpu->arch.fp.fpscr, &ps0_out, &ps0_in1, &ps0_in2, &ps0_in3);
|
|
|
|
dprintk(KERN_INFO "PS3 ps0 -> f(0x%x, 0x%x, 0x%x) = 0x%x\n",
|
|
ps0_in1, ps0_in2, ps0_in3, ps0_out);
|
|
|
|
if (!(scalar & SCALAR_NO_PS0))
|
|
kvm_cvt_fd(&ps0_out, &VCPU_FPR(vcpu, reg_out));
|
|
|
|
/* PS1 */
|
|
ps1_in1 = qpr[reg_in1];
|
|
ps1_in2 = qpr[reg_in2];
|
|
ps1_in3 = qpr[reg_in3];
|
|
|
|
if (scalar & SCALAR_HIGH)
|
|
ps1_in2 = ps0_in2;
|
|
|
|
if (!(scalar & SCALAR_NO_PS1))
|
|
func(&vcpu->arch.fp.fpscr, &qpr[reg_out], &ps1_in1, &ps1_in2, &ps1_in3);
|
|
|
|
dprintk(KERN_INFO "PS3 ps1 -> f(0x%x, 0x%x, 0x%x) = 0x%x\n",
|
|
ps1_in1, ps1_in2, ps1_in3, qpr[reg_out]);
|
|
|
|
return EMULATE_DONE;
|
|
}
|
|
|
|
static int kvmppc_ps_two_in(struct kvm_vcpu *vcpu, bool rc,
|
|
int reg_out, int reg_in1, int reg_in2,
|
|
int scalar,
|
|
void (*func)(u64 *fpscr,
|
|
u32 *dst, u32 *src1,
|
|
u32 *src2))
|
|
{
|
|
u32 *qpr = vcpu->arch.qpr;
|
|
u32 ps0_out;
|
|
u32 ps0_in1, ps0_in2;
|
|
u32 ps1_out;
|
|
u32 ps1_in1, ps1_in2;
|
|
|
|
/* RC */
|
|
WARN_ON(rc);
|
|
|
|
/* PS0 */
|
|
kvm_cvt_df(&VCPU_FPR(vcpu, reg_in1), &ps0_in1);
|
|
|
|
if (scalar & SCALAR_LOW)
|
|
ps0_in2 = qpr[reg_in2];
|
|
else
|
|
kvm_cvt_df(&VCPU_FPR(vcpu, reg_in2), &ps0_in2);
|
|
|
|
func(&vcpu->arch.fp.fpscr, &ps0_out, &ps0_in1, &ps0_in2);
|
|
|
|
if (!(scalar & SCALAR_NO_PS0)) {
|
|
dprintk(KERN_INFO "PS2 ps0 -> f(0x%x, 0x%x) = 0x%x\n",
|
|
ps0_in1, ps0_in2, ps0_out);
|
|
|
|
kvm_cvt_fd(&ps0_out, &VCPU_FPR(vcpu, reg_out));
|
|
}
|
|
|
|
/* PS1 */
|
|
ps1_in1 = qpr[reg_in1];
|
|
ps1_in2 = qpr[reg_in2];
|
|
|
|
if (scalar & SCALAR_HIGH)
|
|
ps1_in2 = ps0_in2;
|
|
|
|
func(&vcpu->arch.fp.fpscr, &ps1_out, &ps1_in1, &ps1_in2);
|
|
|
|
if (!(scalar & SCALAR_NO_PS1)) {
|
|
qpr[reg_out] = ps1_out;
|
|
|
|
dprintk(KERN_INFO "PS2 ps1 -> f(0x%x, 0x%x) = 0x%x\n",
|
|
ps1_in1, ps1_in2, qpr[reg_out]);
|
|
}
|
|
|
|
return EMULATE_DONE;
|
|
}
|
|
|
|
static int kvmppc_ps_one_in(struct kvm_vcpu *vcpu, bool rc,
|
|
int reg_out, int reg_in,
|
|
void (*func)(u64 *t,
|
|
u32 *dst, u32 *src1))
|
|
{
|
|
u32 *qpr = vcpu->arch.qpr;
|
|
u32 ps0_out, ps0_in;
|
|
u32 ps1_in;
|
|
|
|
/* RC */
|
|
WARN_ON(rc);
|
|
|
|
/* PS0 */
|
|
kvm_cvt_df(&VCPU_FPR(vcpu, reg_in), &ps0_in);
|
|
func(&vcpu->arch.fp.fpscr, &ps0_out, &ps0_in);
|
|
|
|
dprintk(KERN_INFO "PS1 ps0 -> f(0x%x) = 0x%x\n",
|
|
ps0_in, ps0_out);
|
|
|
|
kvm_cvt_fd(&ps0_out, &VCPU_FPR(vcpu, reg_out));
|
|
|
|
/* PS1 */
|
|
ps1_in = qpr[reg_in];
|
|
func(&vcpu->arch.fp.fpscr, &qpr[reg_out], &ps1_in);
|
|
|
|
dprintk(KERN_INFO "PS1 ps1 -> f(0x%x) = 0x%x\n",
|
|
ps1_in, qpr[reg_out]);
|
|
|
|
return EMULATE_DONE;
|
|
}
|
|
|
|
int kvmppc_emulate_paired_single(struct kvm_run *run, struct kvm_vcpu *vcpu)
|
|
{
|
|
u32 inst;
|
|
enum emulation_result emulated = EMULATE_DONE;
|
|
int ax_rd, ax_ra, ax_rb, ax_rc;
|
|
short full_d;
|
|
u64 *fpr_d, *fpr_a, *fpr_b, *fpr_c;
|
|
|
|
bool rcomp;
|
|
u32 cr;
|
|
#ifdef DEBUG
|
|
int i;
|
|
#endif
|
|
|
|
emulated = kvmppc_get_last_inst(vcpu, INST_GENERIC, &inst);
|
|
if (emulated != EMULATE_DONE)
|
|
return emulated;
|
|
|
|
ax_rd = inst_get_field(inst, 6, 10);
|
|
ax_ra = inst_get_field(inst, 11, 15);
|
|
ax_rb = inst_get_field(inst, 16, 20);
|
|
ax_rc = inst_get_field(inst, 21, 25);
|
|
full_d = inst_get_field(inst, 16, 31);
|
|
|
|
fpr_d = &VCPU_FPR(vcpu, ax_rd);
|
|
fpr_a = &VCPU_FPR(vcpu, ax_ra);
|
|
fpr_b = &VCPU_FPR(vcpu, ax_rb);
|
|
fpr_c = &VCPU_FPR(vcpu, ax_rc);
|
|
|
|
rcomp = (inst & 1) ? true : false;
|
|
cr = kvmppc_get_cr(vcpu);
|
|
|
|
if (!kvmppc_inst_is_paired_single(vcpu, inst))
|
|
return EMULATE_FAIL;
|
|
|
|
if (!(kvmppc_get_msr(vcpu) & MSR_FP)) {
|
|
kvmppc_book3s_queue_irqprio(vcpu, BOOK3S_INTERRUPT_FP_UNAVAIL);
|
|
return EMULATE_AGAIN;
|
|
}
|
|
|
|
kvmppc_giveup_ext(vcpu, MSR_FP);
|
|
preempt_disable();
|
|
enable_kernel_fp();
|
|
/* Do we need to clear FE0 / FE1 here? Don't think so. */
|
|
|
|
#ifdef DEBUG
|
|
for (i = 0; i < ARRAY_SIZE(vcpu->arch.fp.fpr); i++) {
|
|
u32 f;
|
|
kvm_cvt_df(&VCPU_FPR(vcpu, i), &f);
|
|
dprintk(KERN_INFO "FPR[%d] = 0x%x / 0x%llx QPR[%d] = 0x%x\n",
|
|
i, f, VCPU_FPR(vcpu, i), i, vcpu->arch.qpr[i]);
|
|
}
|
|
#endif
|
|
|
|
switch (get_op(inst)) {
|
|
case OP_PSQ_L:
|
|
{
|
|
ulong addr = ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0;
|
|
bool w = inst_get_field(inst, 16, 16) ? true : false;
|
|
int i = inst_get_field(inst, 17, 19);
|
|
|
|
addr += get_d_signext(inst);
|
|
emulated = kvmppc_emulate_psq_load(run, vcpu, ax_rd, addr, w, i);
|
|
break;
|
|
}
|
|
case OP_PSQ_LU:
|
|
{
|
|
ulong addr = kvmppc_get_gpr(vcpu, ax_ra);
|
|
bool w = inst_get_field(inst, 16, 16) ? true : false;
|
|
int i = inst_get_field(inst, 17, 19);
|
|
|
|
addr += get_d_signext(inst);
|
|
emulated = kvmppc_emulate_psq_load(run, vcpu, ax_rd, addr, w, i);
|
|
|
|
if (emulated == EMULATE_DONE)
|
|
kvmppc_set_gpr(vcpu, ax_ra, addr);
|
|
break;
|
|
}
|
|
case OP_PSQ_ST:
|
|
{
|
|
ulong addr = ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0;
|
|
bool w = inst_get_field(inst, 16, 16) ? true : false;
|
|
int i = inst_get_field(inst, 17, 19);
|
|
|
|
addr += get_d_signext(inst);
|
|
emulated = kvmppc_emulate_psq_store(run, vcpu, ax_rd, addr, w, i);
|
|
break;
|
|
}
|
|
case OP_PSQ_STU:
|
|
{
|
|
ulong addr = kvmppc_get_gpr(vcpu, ax_ra);
|
|
bool w = inst_get_field(inst, 16, 16) ? true : false;
|
|
int i = inst_get_field(inst, 17, 19);
|
|
|
|
addr += get_d_signext(inst);
|
|
emulated = kvmppc_emulate_psq_store(run, vcpu, ax_rd, addr, w, i);
|
|
|
|
if (emulated == EMULATE_DONE)
|
|
kvmppc_set_gpr(vcpu, ax_ra, addr);
|
|
break;
|
|
}
|
|
case 4:
|
|
/* X form */
|
|
switch (inst_get_field(inst, 21, 30)) {
|
|
case OP_4X_PS_CMPU0:
|
|
/* XXX */
|
|
emulated = EMULATE_FAIL;
|
|
break;
|
|
case OP_4X_PSQ_LX:
|
|
{
|
|
ulong addr = ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0;
|
|
bool w = inst_get_field(inst, 21, 21) ? true : false;
|
|
int i = inst_get_field(inst, 22, 24);
|
|
|
|
addr += kvmppc_get_gpr(vcpu, ax_rb);
|
|
emulated = kvmppc_emulate_psq_load(run, vcpu, ax_rd, addr, w, i);
|
|
break;
|
|
}
|
|
case OP_4X_PS_CMPO0:
|
|
/* XXX */
|
|
emulated = EMULATE_FAIL;
|
|
break;
|
|
case OP_4X_PSQ_LUX:
|
|
{
|
|
ulong addr = kvmppc_get_gpr(vcpu, ax_ra);
|
|
bool w = inst_get_field(inst, 21, 21) ? true : false;
|
|
int i = inst_get_field(inst, 22, 24);
|
|
|
|
addr += kvmppc_get_gpr(vcpu, ax_rb);
|
|
emulated = kvmppc_emulate_psq_load(run, vcpu, ax_rd, addr, w, i);
|
|
|
|
if (emulated == EMULATE_DONE)
|
|
kvmppc_set_gpr(vcpu, ax_ra, addr);
|
|
break;
|
|
}
|
|
case OP_4X_PS_NEG:
|
|
VCPU_FPR(vcpu, ax_rd) = VCPU_FPR(vcpu, ax_rb);
|
|
VCPU_FPR(vcpu, ax_rd) ^= 0x8000000000000000ULL;
|
|
vcpu->arch.qpr[ax_rd] = vcpu->arch.qpr[ax_rb];
|
|
vcpu->arch.qpr[ax_rd] ^= 0x80000000;
|
|
break;
|
|
case OP_4X_PS_CMPU1:
|
|
/* XXX */
|
|
emulated = EMULATE_FAIL;
|
|
break;
|
|
case OP_4X_PS_MR:
|
|
WARN_ON(rcomp);
|
|
VCPU_FPR(vcpu, ax_rd) = VCPU_FPR(vcpu, ax_rb);
|
|
vcpu->arch.qpr[ax_rd] = vcpu->arch.qpr[ax_rb];
|
|
break;
|
|
case OP_4X_PS_CMPO1:
|
|
/* XXX */
|
|
emulated = EMULATE_FAIL;
|
|
break;
|
|
case OP_4X_PS_NABS:
|
|
WARN_ON(rcomp);
|
|
VCPU_FPR(vcpu, ax_rd) = VCPU_FPR(vcpu, ax_rb);
|
|
VCPU_FPR(vcpu, ax_rd) |= 0x8000000000000000ULL;
|
|
vcpu->arch.qpr[ax_rd] = vcpu->arch.qpr[ax_rb];
|
|
vcpu->arch.qpr[ax_rd] |= 0x80000000;
|
|
break;
|
|
case OP_4X_PS_ABS:
|
|
WARN_ON(rcomp);
|
|
VCPU_FPR(vcpu, ax_rd) = VCPU_FPR(vcpu, ax_rb);
|
|
VCPU_FPR(vcpu, ax_rd) &= ~0x8000000000000000ULL;
|
|
vcpu->arch.qpr[ax_rd] = vcpu->arch.qpr[ax_rb];
|
|
vcpu->arch.qpr[ax_rd] &= ~0x80000000;
|
|
break;
|
|
case OP_4X_PS_MERGE00:
|
|
WARN_ON(rcomp);
|
|
VCPU_FPR(vcpu, ax_rd) = VCPU_FPR(vcpu, ax_ra);
|
|
/* vcpu->arch.qpr[ax_rd] = VCPU_FPR(vcpu, ax_rb); */
|
|
kvm_cvt_df(&VCPU_FPR(vcpu, ax_rb),
|
|
&vcpu->arch.qpr[ax_rd]);
|
|
break;
|
|
case OP_4X_PS_MERGE01:
|
|
WARN_ON(rcomp);
|
|
VCPU_FPR(vcpu, ax_rd) = VCPU_FPR(vcpu, ax_ra);
|
|
vcpu->arch.qpr[ax_rd] = vcpu->arch.qpr[ax_rb];
|
|
break;
|
|
case OP_4X_PS_MERGE10:
|
|
WARN_ON(rcomp);
|
|
/* VCPU_FPR(vcpu, ax_rd) = vcpu->arch.qpr[ax_ra]; */
|
|
kvm_cvt_fd(&vcpu->arch.qpr[ax_ra],
|
|
&VCPU_FPR(vcpu, ax_rd));
|
|
/* vcpu->arch.qpr[ax_rd] = VCPU_FPR(vcpu, ax_rb); */
|
|
kvm_cvt_df(&VCPU_FPR(vcpu, ax_rb),
|
|
&vcpu->arch.qpr[ax_rd]);
|
|
break;
|
|
case OP_4X_PS_MERGE11:
|
|
WARN_ON(rcomp);
|
|
/* VCPU_FPR(vcpu, ax_rd) = vcpu->arch.qpr[ax_ra]; */
|
|
kvm_cvt_fd(&vcpu->arch.qpr[ax_ra],
|
|
&VCPU_FPR(vcpu, ax_rd));
|
|
vcpu->arch.qpr[ax_rd] = vcpu->arch.qpr[ax_rb];
|
|
break;
|
|
}
|
|
/* XW form */
|
|
switch (inst_get_field(inst, 25, 30)) {
|
|
case OP_4XW_PSQ_STX:
|
|
{
|
|
ulong addr = ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0;
|
|
bool w = inst_get_field(inst, 21, 21) ? true : false;
|
|
int i = inst_get_field(inst, 22, 24);
|
|
|
|
addr += kvmppc_get_gpr(vcpu, ax_rb);
|
|
emulated = kvmppc_emulate_psq_store(run, vcpu, ax_rd, addr, w, i);
|
|
break;
|
|
}
|
|
case OP_4XW_PSQ_STUX:
|
|
{
|
|
ulong addr = kvmppc_get_gpr(vcpu, ax_ra);
|
|
bool w = inst_get_field(inst, 21, 21) ? true : false;
|
|
int i = inst_get_field(inst, 22, 24);
|
|
|
|
addr += kvmppc_get_gpr(vcpu, ax_rb);
|
|
emulated = kvmppc_emulate_psq_store(run, vcpu, ax_rd, addr, w, i);
|
|
|
|
if (emulated == EMULATE_DONE)
|
|
kvmppc_set_gpr(vcpu, ax_ra, addr);
|
|
break;
|
|
}
|
|
}
|
|
/* A form */
|
|
switch (inst_get_field(inst, 26, 30)) {
|
|
case OP_4A_PS_SUM1:
|
|
emulated = kvmppc_ps_two_in(vcpu, rcomp, ax_rd,
|
|
ax_rb, ax_ra, SCALAR_NO_PS0 | SCALAR_HIGH, fps_fadds);
|
|
VCPU_FPR(vcpu, ax_rd) = VCPU_FPR(vcpu, ax_rc);
|
|
break;
|
|
case OP_4A_PS_SUM0:
|
|
emulated = kvmppc_ps_two_in(vcpu, rcomp, ax_rd,
|
|
ax_ra, ax_rb, SCALAR_NO_PS1 | SCALAR_LOW, fps_fadds);
|
|
vcpu->arch.qpr[ax_rd] = vcpu->arch.qpr[ax_rc];
|
|
break;
|
|
case OP_4A_PS_MULS0:
|
|
emulated = kvmppc_ps_two_in(vcpu, rcomp, ax_rd,
|
|
ax_ra, ax_rc, SCALAR_HIGH, fps_fmuls);
|
|
break;
|
|
case OP_4A_PS_MULS1:
|
|
emulated = kvmppc_ps_two_in(vcpu, rcomp, ax_rd,
|
|
ax_ra, ax_rc, SCALAR_LOW, fps_fmuls);
|
|
break;
|
|
case OP_4A_PS_MADDS0:
|
|
emulated = kvmppc_ps_three_in(vcpu, rcomp, ax_rd,
|
|
ax_ra, ax_rc, ax_rb, SCALAR_HIGH, fps_fmadds);
|
|
break;
|
|
case OP_4A_PS_MADDS1:
|
|
emulated = kvmppc_ps_three_in(vcpu, rcomp, ax_rd,
|
|
ax_ra, ax_rc, ax_rb, SCALAR_LOW, fps_fmadds);
|
|
break;
|
|
case OP_4A_PS_DIV:
|
|
emulated = kvmppc_ps_two_in(vcpu, rcomp, ax_rd,
|
|
ax_ra, ax_rb, SCALAR_NONE, fps_fdivs);
|
|
break;
|
|
case OP_4A_PS_SUB:
|
|
emulated = kvmppc_ps_two_in(vcpu, rcomp, ax_rd,
|
|
ax_ra, ax_rb, SCALAR_NONE, fps_fsubs);
|
|
break;
|
|
case OP_4A_PS_ADD:
|
|
emulated = kvmppc_ps_two_in(vcpu, rcomp, ax_rd,
|
|
ax_ra, ax_rb, SCALAR_NONE, fps_fadds);
|
|
break;
|
|
case OP_4A_PS_SEL:
|
|
emulated = kvmppc_ps_three_in(vcpu, rcomp, ax_rd,
|
|
ax_ra, ax_rc, ax_rb, SCALAR_NONE, fps_fsel);
|
|
break;
|
|
case OP_4A_PS_RES:
|
|
emulated = kvmppc_ps_one_in(vcpu, rcomp, ax_rd,
|
|
ax_rb, fps_fres);
|
|
break;
|
|
case OP_4A_PS_MUL:
|
|
emulated = kvmppc_ps_two_in(vcpu, rcomp, ax_rd,
|
|
ax_ra, ax_rc, SCALAR_NONE, fps_fmuls);
|
|
break;
|
|
case OP_4A_PS_RSQRTE:
|
|
emulated = kvmppc_ps_one_in(vcpu, rcomp, ax_rd,
|
|
ax_rb, fps_frsqrte);
|
|
break;
|
|
case OP_4A_PS_MSUB:
|
|
emulated = kvmppc_ps_three_in(vcpu, rcomp, ax_rd,
|
|
ax_ra, ax_rc, ax_rb, SCALAR_NONE, fps_fmsubs);
|
|
break;
|
|
case OP_4A_PS_MADD:
|
|
emulated = kvmppc_ps_three_in(vcpu, rcomp, ax_rd,
|
|
ax_ra, ax_rc, ax_rb, SCALAR_NONE, fps_fmadds);
|
|
break;
|
|
case OP_4A_PS_NMSUB:
|
|
emulated = kvmppc_ps_three_in(vcpu, rcomp, ax_rd,
|
|
ax_ra, ax_rc, ax_rb, SCALAR_NONE, fps_fnmsubs);
|
|
break;
|
|
case OP_4A_PS_NMADD:
|
|
emulated = kvmppc_ps_three_in(vcpu, rcomp, ax_rd,
|
|
ax_ra, ax_rc, ax_rb, SCALAR_NONE, fps_fnmadds);
|
|
break;
|
|
}
|
|
break;
|
|
|
|
/* Real FPU operations */
|
|
|
|
case OP_LFS:
|
|
{
|
|
ulong addr = (ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0) + full_d;
|
|
|
|
emulated = kvmppc_emulate_fpr_load(run, vcpu, ax_rd, addr,
|
|
FPU_LS_SINGLE);
|
|
break;
|
|
}
|
|
case OP_LFSU:
|
|
{
|
|
ulong addr = kvmppc_get_gpr(vcpu, ax_ra) + full_d;
|
|
|
|
emulated = kvmppc_emulate_fpr_load(run, vcpu, ax_rd, addr,
|
|
FPU_LS_SINGLE);
|
|
|
|
if (emulated == EMULATE_DONE)
|
|
kvmppc_set_gpr(vcpu, ax_ra, addr);
|
|
break;
|
|
}
|
|
case OP_LFD:
|
|
{
|
|
ulong addr = (ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0) + full_d;
|
|
|
|
emulated = kvmppc_emulate_fpr_load(run, vcpu, ax_rd, addr,
|
|
FPU_LS_DOUBLE);
|
|
break;
|
|
}
|
|
case OP_LFDU:
|
|
{
|
|
ulong addr = kvmppc_get_gpr(vcpu, ax_ra) + full_d;
|
|
|
|
emulated = kvmppc_emulate_fpr_load(run, vcpu, ax_rd, addr,
|
|
FPU_LS_DOUBLE);
|
|
|
|
if (emulated == EMULATE_DONE)
|
|
kvmppc_set_gpr(vcpu, ax_ra, addr);
|
|
break;
|
|
}
|
|
case OP_STFS:
|
|
{
|
|
ulong addr = (ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0) + full_d;
|
|
|
|
emulated = kvmppc_emulate_fpr_store(run, vcpu, ax_rd, addr,
|
|
FPU_LS_SINGLE);
|
|
break;
|
|
}
|
|
case OP_STFSU:
|
|
{
|
|
ulong addr = kvmppc_get_gpr(vcpu, ax_ra) + full_d;
|
|
|
|
emulated = kvmppc_emulate_fpr_store(run, vcpu, ax_rd, addr,
|
|
FPU_LS_SINGLE);
|
|
|
|
if (emulated == EMULATE_DONE)
|
|
kvmppc_set_gpr(vcpu, ax_ra, addr);
|
|
break;
|
|
}
|
|
case OP_STFD:
|
|
{
|
|
ulong addr = (ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0) + full_d;
|
|
|
|
emulated = kvmppc_emulate_fpr_store(run, vcpu, ax_rd, addr,
|
|
FPU_LS_DOUBLE);
|
|
break;
|
|
}
|
|
case OP_STFDU:
|
|
{
|
|
ulong addr = kvmppc_get_gpr(vcpu, ax_ra) + full_d;
|
|
|
|
emulated = kvmppc_emulate_fpr_store(run, vcpu, ax_rd, addr,
|
|
FPU_LS_DOUBLE);
|
|
|
|
if (emulated == EMULATE_DONE)
|
|
kvmppc_set_gpr(vcpu, ax_ra, addr);
|
|
break;
|
|
}
|
|
case 31:
|
|
switch (inst_get_field(inst, 21, 30)) {
|
|
case OP_31_LFSX:
|
|
{
|
|
ulong addr = ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0;
|
|
|
|
addr += kvmppc_get_gpr(vcpu, ax_rb);
|
|
emulated = kvmppc_emulate_fpr_load(run, vcpu, ax_rd,
|
|
addr, FPU_LS_SINGLE);
|
|
break;
|
|
}
|
|
case OP_31_LFSUX:
|
|
{
|
|
ulong addr = kvmppc_get_gpr(vcpu, ax_ra) +
|
|
kvmppc_get_gpr(vcpu, ax_rb);
|
|
|
|
emulated = kvmppc_emulate_fpr_load(run, vcpu, ax_rd,
|
|
addr, FPU_LS_SINGLE);
|
|
|
|
if (emulated == EMULATE_DONE)
|
|
kvmppc_set_gpr(vcpu, ax_ra, addr);
|
|
break;
|
|
}
|
|
case OP_31_LFDX:
|
|
{
|
|
ulong addr = (ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0) +
|
|
kvmppc_get_gpr(vcpu, ax_rb);
|
|
|
|
emulated = kvmppc_emulate_fpr_load(run, vcpu, ax_rd,
|
|
addr, FPU_LS_DOUBLE);
|
|
break;
|
|
}
|
|
case OP_31_LFDUX:
|
|
{
|
|
ulong addr = kvmppc_get_gpr(vcpu, ax_ra) +
|
|
kvmppc_get_gpr(vcpu, ax_rb);
|
|
|
|
emulated = kvmppc_emulate_fpr_load(run, vcpu, ax_rd,
|
|
addr, FPU_LS_DOUBLE);
|
|
|
|
if (emulated == EMULATE_DONE)
|
|
kvmppc_set_gpr(vcpu, ax_ra, addr);
|
|
break;
|
|
}
|
|
case OP_31_STFSX:
|
|
{
|
|
ulong addr = (ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0) +
|
|
kvmppc_get_gpr(vcpu, ax_rb);
|
|
|
|
emulated = kvmppc_emulate_fpr_store(run, vcpu, ax_rd,
|
|
addr, FPU_LS_SINGLE);
|
|
break;
|
|
}
|
|
case OP_31_STFSUX:
|
|
{
|
|
ulong addr = kvmppc_get_gpr(vcpu, ax_ra) +
|
|
kvmppc_get_gpr(vcpu, ax_rb);
|
|
|
|
emulated = kvmppc_emulate_fpr_store(run, vcpu, ax_rd,
|
|
addr, FPU_LS_SINGLE);
|
|
|
|
if (emulated == EMULATE_DONE)
|
|
kvmppc_set_gpr(vcpu, ax_ra, addr);
|
|
break;
|
|
}
|
|
case OP_31_STFX:
|
|
{
|
|
ulong addr = (ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0) +
|
|
kvmppc_get_gpr(vcpu, ax_rb);
|
|
|
|
emulated = kvmppc_emulate_fpr_store(run, vcpu, ax_rd,
|
|
addr, FPU_LS_DOUBLE);
|
|
break;
|
|
}
|
|
case OP_31_STFUX:
|
|
{
|
|
ulong addr = kvmppc_get_gpr(vcpu, ax_ra) +
|
|
kvmppc_get_gpr(vcpu, ax_rb);
|
|
|
|
emulated = kvmppc_emulate_fpr_store(run, vcpu, ax_rd,
|
|
addr, FPU_LS_DOUBLE);
|
|
|
|
if (emulated == EMULATE_DONE)
|
|
kvmppc_set_gpr(vcpu, ax_ra, addr);
|
|
break;
|
|
}
|
|
case OP_31_STFIWX:
|
|
{
|
|
ulong addr = (ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0) +
|
|
kvmppc_get_gpr(vcpu, ax_rb);
|
|
|
|
emulated = kvmppc_emulate_fpr_store(run, vcpu, ax_rd,
|
|
addr,
|
|
FPU_LS_SINGLE_LOW);
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
break;
|
|
case 59:
|
|
switch (inst_get_field(inst, 21, 30)) {
|
|
case OP_59_FADDS:
|
|
fpd_fadds(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_a, fpr_b);
|
|
kvmppc_sync_qpr(vcpu, ax_rd);
|
|
break;
|
|
case OP_59_FSUBS:
|
|
fpd_fsubs(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_a, fpr_b);
|
|
kvmppc_sync_qpr(vcpu, ax_rd);
|
|
break;
|
|
case OP_59_FDIVS:
|
|
fpd_fdivs(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_a, fpr_b);
|
|
kvmppc_sync_qpr(vcpu, ax_rd);
|
|
break;
|
|
case OP_59_FRES:
|
|
fpd_fres(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_b);
|
|
kvmppc_sync_qpr(vcpu, ax_rd);
|
|
break;
|
|
case OP_59_FRSQRTES:
|
|
fpd_frsqrtes(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_b);
|
|
kvmppc_sync_qpr(vcpu, ax_rd);
|
|
break;
|
|
}
|
|
switch (inst_get_field(inst, 26, 30)) {
|
|
case OP_59_FMULS:
|
|
fpd_fmuls(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_a, fpr_c);
|
|
kvmppc_sync_qpr(vcpu, ax_rd);
|
|
break;
|
|
case OP_59_FMSUBS:
|
|
fpd_fmsubs(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b);
|
|
kvmppc_sync_qpr(vcpu, ax_rd);
|
|
break;
|
|
case OP_59_FMADDS:
|
|
fpd_fmadds(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b);
|
|
kvmppc_sync_qpr(vcpu, ax_rd);
|
|
break;
|
|
case OP_59_FNMSUBS:
|
|
fpd_fnmsubs(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b);
|
|
kvmppc_sync_qpr(vcpu, ax_rd);
|
|
break;
|
|
case OP_59_FNMADDS:
|
|
fpd_fnmadds(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b);
|
|
kvmppc_sync_qpr(vcpu, ax_rd);
|
|
break;
|
|
}
|
|
break;
|
|
case 63:
|
|
switch (inst_get_field(inst, 21, 30)) {
|
|
case OP_63_MTFSB0:
|
|
case OP_63_MTFSB1:
|
|
case OP_63_MCRFS:
|
|
case OP_63_MTFSFI:
|
|
/* XXX need to implement */
|
|
break;
|
|
case OP_63_MFFS:
|
|
/* XXX missing CR */
|
|
*fpr_d = vcpu->arch.fp.fpscr;
|
|
break;
|
|
case OP_63_MTFSF:
|
|
/* XXX missing fm bits */
|
|
/* XXX missing CR */
|
|
vcpu->arch.fp.fpscr = *fpr_b;
|
|
break;
|
|
case OP_63_FCMPU:
|
|
{
|
|
u32 tmp_cr;
|
|
u32 cr0_mask = 0xf0000000;
|
|
u32 cr_shift = inst_get_field(inst, 6, 8) * 4;
|
|
|
|
fpd_fcmpu(&vcpu->arch.fp.fpscr, &tmp_cr, fpr_a, fpr_b);
|
|
cr &= ~(cr0_mask >> cr_shift);
|
|
cr |= (cr & cr0_mask) >> cr_shift;
|
|
break;
|
|
}
|
|
case OP_63_FCMPO:
|
|
{
|
|
u32 tmp_cr;
|
|
u32 cr0_mask = 0xf0000000;
|
|
u32 cr_shift = inst_get_field(inst, 6, 8) * 4;
|
|
|
|
fpd_fcmpo(&vcpu->arch.fp.fpscr, &tmp_cr, fpr_a, fpr_b);
|
|
cr &= ~(cr0_mask >> cr_shift);
|
|
cr |= (cr & cr0_mask) >> cr_shift;
|
|
break;
|
|
}
|
|
case OP_63_FNEG:
|
|
fpd_fneg(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_b);
|
|
break;
|
|
case OP_63_FMR:
|
|
*fpr_d = *fpr_b;
|
|
break;
|
|
case OP_63_FABS:
|
|
fpd_fabs(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_b);
|
|
break;
|
|
case OP_63_FCPSGN:
|
|
fpd_fcpsgn(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_a, fpr_b);
|
|
break;
|
|
case OP_63_FDIV:
|
|
fpd_fdiv(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_a, fpr_b);
|
|
break;
|
|
case OP_63_FADD:
|
|
fpd_fadd(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_a, fpr_b);
|
|
break;
|
|
case OP_63_FSUB:
|
|
fpd_fsub(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_a, fpr_b);
|
|
break;
|
|
case OP_63_FCTIW:
|
|
fpd_fctiw(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_b);
|
|
break;
|
|
case OP_63_FCTIWZ:
|
|
fpd_fctiwz(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_b);
|
|
break;
|
|
case OP_63_FRSP:
|
|
fpd_frsp(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_b);
|
|
kvmppc_sync_qpr(vcpu, ax_rd);
|
|
break;
|
|
case OP_63_FRSQRTE:
|
|
{
|
|
double one = 1.0f;
|
|
|
|
/* fD = sqrt(fB) */
|
|
fpd_fsqrt(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_b);
|
|
/* fD = 1.0f / fD */
|
|
fpd_fdiv(&vcpu->arch.fp.fpscr, &cr, fpr_d, (u64*)&one, fpr_d);
|
|
break;
|
|
}
|
|
}
|
|
switch (inst_get_field(inst, 26, 30)) {
|
|
case OP_63_FMUL:
|
|
fpd_fmul(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_a, fpr_c);
|
|
break;
|
|
case OP_63_FSEL:
|
|
fpd_fsel(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b);
|
|
break;
|
|
case OP_63_FMSUB:
|
|
fpd_fmsub(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b);
|
|
break;
|
|
case OP_63_FMADD:
|
|
fpd_fmadd(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b);
|
|
break;
|
|
case OP_63_FNMSUB:
|
|
fpd_fnmsub(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b);
|
|
break;
|
|
case OP_63_FNMADD:
|
|
fpd_fnmadd(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b);
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
|
|
#ifdef DEBUG
|
|
for (i = 0; i < ARRAY_SIZE(vcpu->arch.fp.fpr); i++) {
|
|
u32 f;
|
|
kvm_cvt_df(&VCPU_FPR(vcpu, i), &f);
|
|
dprintk(KERN_INFO "FPR[%d] = 0x%x\n", i, f);
|
|
}
|
|
#endif
|
|
|
|
if (rcomp)
|
|
kvmppc_set_cr(vcpu, cr);
|
|
|
|
preempt_enable();
|
|
|
|
return emulated;
|
|
}
|