371 lines
10 KiB
C
371 lines
10 KiB
C
/*
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* Setup pointers to hardware-dependent routines.
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* Copyright (C) 2000-2001 Toshiba Corporation
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*
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* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
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* terms of the GNU General Public License version 2. This program is
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* licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*
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* Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
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*/
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/ioport.h>
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#include <linux/delay.h>
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#include <linux/platform_device.h>
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#include <linux/gpio.h>
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#include <linux/mtd/physmap.h>
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#include <asm/reboot.h>
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#include <asm/io.h>
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#include <asm/txx9/generic.h>
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#include <asm/txx9/pci.h>
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#include <asm/txx9/rbtx4938.h>
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#include <linux/spi/spi.h>
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#include <asm/txx9/spi.h>
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#include <asm/txx9pio.h>
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static void rbtx4938_machine_restart(char *command)
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{
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local_irq_disable();
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writeb(1, rbtx4938_softresetlock_addr);
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writeb(1, rbtx4938_sfvol_addr);
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writeb(1, rbtx4938_softreset_addr);
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/* fallback */
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(*_machine_halt)();
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}
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static void __init rbtx4938_pci_setup(void)
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{
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#ifdef CONFIG_PCI
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int extarb = !(__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB);
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struct pci_controller *c = &txx9_primary_pcic;
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register_pci_controller(c);
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if (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66)
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txx9_pci_option =
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(txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) |
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TXX9_PCI_OPT_CLK_66; /* already configured */
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/* Reset PCI Bus */
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writeb(0, rbtx4938_pcireset_addr);
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/* Reset PCIC */
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txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
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if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
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TXX9_PCI_OPT_CLK_66)
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tx4938_pciclk66_setup();
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mdelay(10);
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/* clear PCIC reset */
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txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
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writeb(1, rbtx4938_pcireset_addr);
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iob();
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tx4938_report_pciclk();
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tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
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if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
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TXX9_PCI_OPT_CLK_AUTO &&
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txx9_pci66_check(c, 0, 0)) {
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/* Reset PCI Bus */
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writeb(0, rbtx4938_pcireset_addr);
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/* Reset PCIC */
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txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
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tx4938_pciclk66_setup();
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mdelay(10);
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/* clear PCIC reset */
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txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
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writeb(1, rbtx4938_pcireset_addr);
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iob();
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/* Reinitialize PCIC */
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tx4938_report_pciclk();
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tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
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}
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if (__raw_readq(&tx4938_ccfgptr->pcfg) &
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(TX4938_PCFG_ETH0_SEL|TX4938_PCFG_ETH1_SEL)) {
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/* Reset PCIC1 */
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txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST);
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/* PCI1DMD==0 => PCI1CLK==GBUSCLK/2 => PCI66 */
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if (!(__raw_readq(&tx4938_ccfgptr->ccfg)
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& TX4938_CCFG_PCI1DMD))
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tx4938_ccfg_set(TX4938_CCFG_PCI1_66);
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mdelay(10);
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/* clear PCIC1 reset */
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txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST);
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tx4938_report_pci1clk();
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/* mem:64K(max), io:64K(max) (enough for ETH0,ETH1) */
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c = txx9_alloc_pci_controller(NULL, 0, 0x10000, 0, 0x10000);
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register_pci_controller(c);
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tx4927_pcic_setup(tx4938_pcic1ptr, c, 0);
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}
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tx4938_setup_pcierr_irq();
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#endif /* CONFIG_PCI */
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}
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/* SPI support */
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/* chip select for SPI devices */
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#define SEEPROM1_CS 7 /* PIO7 */
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#define SEEPROM2_CS 0 /* IOC */
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#define SEEPROM3_CS 1 /* IOC */
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#define SRTC_CS 2 /* IOC */
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#define SPI_BUSNO 0
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static int __init rbtx4938_ethaddr_init(void)
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{
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#ifdef CONFIG_PCI
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unsigned char dat[17];
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unsigned char sum;
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int i;
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/* 0-3: "MAC\0", 4-9:eth0, 10-15:eth1, 16:sum */
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if (spi_eeprom_read(SPI_BUSNO, SEEPROM1_CS, 0, dat, sizeof(dat))) {
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printk(KERN_ERR "seeprom: read error.\n");
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return -ENODEV;
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} else {
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if (strcmp(dat, "MAC") != 0)
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printk(KERN_WARNING "seeprom: bad signature.\n");
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for (i = 0, sum = 0; i < sizeof(dat); i++)
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sum += dat[i];
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if (sum)
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printk(KERN_WARNING "seeprom: bad checksum.\n");
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}
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tx4938_ethaddr_init(&dat[4], &dat[4 + 6]);
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#endif /* CONFIG_PCI */
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return 0;
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}
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static void __init rbtx4938_spi_setup(void)
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{
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/* set SPI_SEL */
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txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_SPI_SEL);
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}
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static struct resource rbtx4938_fpga_resource;
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static void __init rbtx4938_time_init(void)
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{
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tx4938_time_init(0);
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}
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static void __init rbtx4938_mem_setup(void)
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{
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unsigned long long pcfg;
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if (txx9_master_clock == 0)
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txx9_master_clock = 25000000; /* 25MHz */
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tx4938_setup();
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#ifdef CONFIG_PCI
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txx9_alloc_pci_controller(&txx9_primary_pcic, 0, 0, 0, 0);
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txx9_board_pcibios_setup = tx4927_pcibios_setup;
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#else
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set_io_port_base(RBTX4938_ETHER_BASE);
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#endif
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tx4938_sio_init(7372800, 0);
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#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61
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pr_info("PIOSEL: disabling both ATA and NAND selection\n");
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txx9_clear64(&tx4938_ccfgptr->pcfg,
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TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL);
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#endif
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#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND
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pr_info("PIOSEL: enabling NAND selection\n");
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txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL);
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txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL);
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#endif
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#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA
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pr_info("PIOSEL: enabling ATA selection\n");
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txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL);
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txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL);
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#endif
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#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_KEEP
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pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg);
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pr_info("PIOSEL: NAND %s, ATA %s\n",
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(pcfg & TX4938_PCFG_NDF_SEL) ? "enabled" : "disabled",
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(pcfg & TX4938_PCFG_ATA_SEL) ? "enabled" : "disabled");
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#endif
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rbtx4938_spi_setup();
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pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg); /* updated */
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/* fixup piosel */
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if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
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TX4938_PCFG_ATA_SEL)
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writeb((readb(rbtx4938_piosel_addr) & 0x03) | 0x04,
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rbtx4938_piosel_addr);
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else if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
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TX4938_PCFG_NDF_SEL)
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writeb((readb(rbtx4938_piosel_addr) & 0x03) | 0x08,
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rbtx4938_piosel_addr);
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else
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writeb(readb(rbtx4938_piosel_addr) & ~(0x08 | 0x04),
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rbtx4938_piosel_addr);
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rbtx4938_fpga_resource.name = "FPGA Registers";
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rbtx4938_fpga_resource.start = CPHYSADDR(RBTX4938_FPGA_REG_ADDR);
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rbtx4938_fpga_resource.end = CPHYSADDR(RBTX4938_FPGA_REG_ADDR) + 0xffff;
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rbtx4938_fpga_resource.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
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if (request_resource(&txx9_ce_res[2], &rbtx4938_fpga_resource))
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printk(KERN_ERR "request resource for fpga failed\n");
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_machine_restart = rbtx4938_machine_restart;
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writeb(0xff, rbtx4938_led_addr);
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printk(KERN_INFO "RBTX4938 --- FPGA(Rev %02x) DIPSW:%02x,%02x\n",
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readb(rbtx4938_fpga_rev_addr),
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readb(rbtx4938_dipsw_addr), readb(rbtx4938_bdipsw_addr));
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}
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static void __init rbtx4938_ne_init(void)
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{
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struct resource res[] = {
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{
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.start = RBTX4938_RTL_8019_BASE,
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.end = RBTX4938_RTL_8019_BASE + 0x20 - 1,
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.flags = IORESOURCE_IO,
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}, {
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.start = RBTX4938_RTL_8019_IRQ,
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.flags = IORESOURCE_IRQ,
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}
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};
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platform_device_register_simple("ne", -1, res, ARRAY_SIZE(res));
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}
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static DEFINE_SPINLOCK(rbtx4938_spi_gpio_lock);
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static void rbtx4938_spi_gpio_set(struct gpio_chip *chip, unsigned int offset,
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int value)
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{
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u8 val;
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unsigned long flags;
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spin_lock_irqsave(&rbtx4938_spi_gpio_lock, flags);
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val = readb(rbtx4938_spics_addr);
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if (value)
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val |= 1 << offset;
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else
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val &= ~(1 << offset);
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writeb(val, rbtx4938_spics_addr);
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mmiowb();
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spin_unlock_irqrestore(&rbtx4938_spi_gpio_lock, flags);
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}
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static int rbtx4938_spi_gpio_dir_out(struct gpio_chip *chip,
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unsigned int offset, int value)
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{
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rbtx4938_spi_gpio_set(chip, offset, value);
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return 0;
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}
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static struct gpio_chip rbtx4938_spi_gpio_chip = {
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.set = rbtx4938_spi_gpio_set,
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.direction_output = rbtx4938_spi_gpio_dir_out,
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.label = "RBTX4938-SPICS",
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.base = 16,
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.ngpio = 3,
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};
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static int __init rbtx4938_spi_init(void)
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{
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struct spi_board_info srtc_info = {
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.modalias = "rtc-rs5c348",
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.max_speed_hz = 1000000, /* 1.0Mbps @ Vdd 2.0V */
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.bus_num = 0,
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.chip_select = 16 + SRTC_CS,
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/* Mode 1 (High-Active, Shift-Then-Sample), High Avtive CS */
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.mode = SPI_MODE_1 | SPI_CS_HIGH,
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};
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spi_register_board_info(&srtc_info, 1);
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spi_eeprom_register(SPI_BUSNO, SEEPROM1_CS, 128);
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spi_eeprom_register(SPI_BUSNO, 16 + SEEPROM2_CS, 128);
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spi_eeprom_register(SPI_BUSNO, 16 + SEEPROM3_CS, 128);
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gpio_request(16 + SRTC_CS, "rtc-rs5c348");
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gpio_direction_output(16 + SRTC_CS, 0);
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gpio_request(SEEPROM1_CS, "seeprom1");
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gpio_direction_output(SEEPROM1_CS, 1);
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gpio_request(16 + SEEPROM2_CS, "seeprom2");
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gpio_direction_output(16 + SEEPROM2_CS, 1);
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gpio_request(16 + SEEPROM3_CS, "seeprom3");
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gpio_direction_output(16 + SEEPROM3_CS, 1);
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tx4938_spi_init(SPI_BUSNO);
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return 0;
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}
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static void __init rbtx4938_mtd_init(void)
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{
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struct physmap_flash_data pdata = {
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.width = 4,
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};
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switch (readb(rbtx4938_bdipsw_addr) & 7) {
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case 0:
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/* Boot */
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txx9_physmap_flash_init(0, 0x1fc00000, 0x400000, &pdata);
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/* System */
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txx9_physmap_flash_init(1, 0x1e000000, 0x1000000, &pdata);
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break;
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case 1:
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/* System */
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txx9_physmap_flash_init(0, 0x1f000000, 0x1000000, &pdata);
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/* Boot */
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txx9_physmap_flash_init(1, 0x1ec00000, 0x400000, &pdata);
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break;
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case 2:
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/* Ext */
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txx9_physmap_flash_init(0, 0x1f000000, 0x1000000, &pdata);
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/* System */
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txx9_physmap_flash_init(1, 0x1e000000, 0x1000000, &pdata);
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/* Boot */
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txx9_physmap_flash_init(2, 0x1dc00000, 0x400000, &pdata);
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break;
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case 3:
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/* Boot */
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txx9_physmap_flash_init(1, 0x1bc00000, 0x400000, &pdata);
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/* System */
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txx9_physmap_flash_init(2, 0x1a000000, 0x1000000, &pdata);
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break;
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}
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}
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static void __init rbtx4938_arch_init(void)
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{
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gpiochip_add(&rbtx4938_spi_gpio_chip);
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rbtx4938_pci_setup();
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rbtx4938_spi_init();
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}
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static void __init rbtx4938_device_init(void)
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{
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rbtx4938_ethaddr_init();
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rbtx4938_ne_init();
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tx4938_wdt_init();
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rbtx4938_mtd_init();
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/* TC58DVM82A1FT: tDH=10ns, tWP=tRP=tREADID=35ns */
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tx4938_ndfmc_init(10, 35);
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tx4938_ata_init(RBTX4938_IRQ_IOC_ATA, 0, 1);
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tx4938_dmac_init(0, 2);
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tx4938_aclc_init();
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platform_device_register_simple("txx9aclc-generic", -1, NULL, 0);
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tx4938_sramc_init();
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txx9_iocled_init(RBTX4938_LED_ADDR - IO_BASE, -1, 8, 1, "green", NULL);
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}
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struct txx9_board_vec rbtx4938_vec __initdata = {
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.system = "Toshiba RBTX4938",
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.prom_init = rbtx4938_prom_init,
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.mem_setup = rbtx4938_mem_setup,
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.irq_setup = rbtx4938_irq_setup,
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.time_init = rbtx4938_time_init,
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.device_init = rbtx4938_device_init,
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.arch_init = rbtx4938_arch_init,
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#ifdef CONFIG_PCI
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.pci_map_irq = rbtx4938_pci_map_irq,
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#endif
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};
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