534 lines
12 KiB
C
534 lines
12 KiB
C
/*
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* Copyright (C) 2002 ARM Ltd.
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* All Rights Reserved
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* Copyright (c) 2010-2016, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/bitops.h>
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#include <linux/cpumask.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/regulator/krait-regulator.h>
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#include <soc/qcom/pm.h>
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#include <soc/qcom/scm-boot.h>
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#include <soc/qcom/cpu_pwr_ctl.h>
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#include <asm/cacheflush.h>
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#include <asm/cputype.h>
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#include <asm/mach-types.h>
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#include <asm/smp_plat.h>
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#include <soc/qcom/socinfo.h>
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#include <mach/hardware.h>
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#include <mach/msm_iomap.h>
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#include "platsmp.h"
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#define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x15A0
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#define SCSS_CPU1CORE_RESET 0xD80
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#define SCSS_DBG_STATUS_CORE_PWRDUP 0xE64
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#define MSM8960_SAW2_BASE_ADDR 0x02089000
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#define APCS_ALIAS0_BASE_ADDR 0xF9088000
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/*
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* Write pen_release in a way that is guaranteed to be visible to all
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* observers, irrespective of whether they're taking part in coherency
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* or not. This is necessary for the hotplug code to work reliably.
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*/
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void __cpuinit write_pen_release(int val)
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{
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pen_release = val;
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smp_wmb();
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__cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
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outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
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}
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static DEFINE_SPINLOCK(boot_lock);
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void __cpuinit msm_secondary_init(unsigned int cpu)
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{
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WARN_ON(msm_platform_secondary_init(cpu));
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/*
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* let the primary processor know we're out of the
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* pen, then head off into the C entry point
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*/
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write_pen_release(-1);
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/*
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* Synchronise with the boot thread.
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*/
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spin_lock(&boot_lock);
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spin_unlock(&boot_lock);
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}
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static int __cpuinit release_secondary_sim(unsigned long base, unsigned int cpu)
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{
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void *base_ptr = ioremap_nocache(base + (cpu * 0x10000), SZ_4K);
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if (!base_ptr)
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return -ENODEV;
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writel_relaxed(0x800, base_ptr+0x04);
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writel_relaxed(0x3FFF, base_ptr+0x14);
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mb();
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iounmap(base_ptr);
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return 0;
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}
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static int __cpuinit scorpion_release_secondary(void)
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{
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void *base_ptr = ioremap_nocache(0x00902000, SZ_4K*2);
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if (!base_ptr)
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return -EINVAL;
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writel_relaxed(0, base_ptr + VDD_SC1_ARRAY_CLAMP_GFS_CTL);
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dmb();
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writel_relaxed(0, base_ptr + SCSS_CPU1CORE_RESET);
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writel_relaxed(3, base_ptr + SCSS_DBG_STATUS_CORE_PWRDUP);
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mb();
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iounmap(base_ptr);
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return 0;
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}
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static int __cpuinit msm8960_release_secondary(unsigned long base,
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unsigned int cpu)
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{
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void *base_ptr = ioremap_nocache(base + (cpu * 0x10000), SZ_4K);
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if (!base_ptr)
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return -ENODEV;
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writel_relaxed(0x109, base_ptr+0x04);
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writel_relaxed(0x101, base_ptr+0x04);
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mb();
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ndelay(300);
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writel_relaxed(0x121, base_ptr+0x04);
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mb();
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udelay(2);
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writel_relaxed(0x120, base_ptr+0x04);
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mb();
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udelay(2);
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writel_relaxed(0x100, base_ptr+0x04);
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mb();
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udelay(100);
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writel_relaxed(0x180, base_ptr+0x04);
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mb();
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iounmap(base_ptr);
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return 0;
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}
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static int __cpuinit msm8974_release_secondary(unsigned long base,
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unsigned int cpu)
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{
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void *base_ptr = ioremap_nocache(base + (cpu * 0x10000), SZ_4K);
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if (!base_ptr)
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return -ENODEV;
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secondary_cpu_hs_init(base_ptr, cpu);
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writel_relaxed(0x021, base_ptr+0x04);
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mb();
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udelay(2);
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writel_relaxed(0x020, base_ptr+0x04);
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mb();
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udelay(2);
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writel_relaxed(0x000, base_ptr+0x04);
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mb();
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writel_relaxed(0x080, base_ptr+0x04);
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mb();
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iounmap(base_ptr);
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return 0;
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}
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static int __cpuinit arm_release_secondary(unsigned long base, unsigned int cpu)
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{
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void *base_ptr = ioremap_nocache(base + (cpu * 0x10000), SZ_4K);
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if (!base_ptr)
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return -ENODEV;
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writel_relaxed(0x00000033, base_ptr+0x04);
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mb();
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writel_relaxed(0x10000001, base_ptr+0x14);
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mb();
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udelay(2);
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writel_relaxed(0x00000031, base_ptr+0x04);
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mb();
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writel_relaxed(0x00000039, base_ptr+0x04);
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mb();
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udelay(2);
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writel_relaxed(0x00020038, base_ptr+0x04);
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mb();
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udelay(2);
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writel_relaxed(0x00020008, base_ptr+0x04);
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mb();
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writel_relaxed(0x00020088, base_ptr+0x04);
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mb();
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iounmap(base_ptr);
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return 0;
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}
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static int __cpuinit release_from_pen(unsigned int cpu)
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{
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unsigned long timeout;
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/* Set preset_lpj to avoid subsequent lpj recalculations */
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preset_lpj = loops_per_jiffy;
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/*
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* set synchronisation state between this boot processor
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* and the secondary one
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*/
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spin_lock(&boot_lock);
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/*
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* The secondary processor is waiting to be released from
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* the holding pen - release it, then wait for it to flag
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* that it has been released by resetting pen_release.
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*
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* Note that "pen_release" is the hardware CPU ID, whereas
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* "cpu" is Linux's internal ID.
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*/
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write_pen_release(cpu_logical_map(cpu));
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/*
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* Send the secondary CPU a soft interrupt, thereby causing
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* the boot monitor to read the system wide flags register,
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* and branch to the address found there.
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*/
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arch_send_wakeup_ipi_mask(cpumask_of(cpu));
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timeout = jiffies + (1 * HZ);
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while (time_before(jiffies, timeout)) {
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smp_rmb();
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if (pen_release == -1)
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break;
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udelay(10);
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}
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/*
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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spin_unlock(&boot_lock);
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return pen_release != -1 ? -ENOSYS : 0;
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}
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DEFINE_PER_CPU(int, cold_boot_done);
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int __cpuinit scorpion_boot_secondary(unsigned int cpu,
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struct task_struct *idle)
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{
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pr_debug("Starting secondary CPU %d\n", cpu);
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if (per_cpu(cold_boot_done, cpu) == false) {
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scorpion_release_secondary();
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per_cpu(cold_boot_done, cpu) = true;
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}
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return release_from_pen(cpu);
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}
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int __cpuinit msm8960_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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pr_debug("Starting secondary CPU %d\n", cpu);
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if (per_cpu(cold_boot_done, cpu) == false) {
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msm8960_release_secondary(0x02088000, cpu);
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per_cpu(cold_boot_done, cpu) = true;
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}
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return release_from_pen(cpu);
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}
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int __cpuinit msm8974_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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pr_debug("Starting secondary CPU %d\n", cpu);
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if (per_cpu(cold_boot_done, cpu) == false) {
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if (of_board_is_sim())
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release_secondary_sim(APCS_ALIAS0_BASE_ADDR, cpu);
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else if (!of_board_is_rumi())
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msm8974_release_secondary(APCS_ALIAS0_BASE_ADDR, cpu);
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per_cpu(cold_boot_done, cpu) = true;
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}
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return release_from_pen(cpu);
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}
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static int __cpuinit msm8916_boot_secondary(unsigned int cpu,
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struct task_struct *idle)
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{
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pr_debug("Starting secondary CPU %d\n", cpu);
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if (per_cpu(cold_boot_done, cpu) == false) {
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if (of_board_is_sim())
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release_secondary_sim(0xb088000, cpu);
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else if (!of_board_is_rumi())
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arm_release_secondary(0xb088000, cpu);
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per_cpu(cold_boot_done, cpu) = true;
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}
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return release_from_pen(cpu);
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}
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static int __cpuinit msm8936_boot_secondary(unsigned int cpu,
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struct task_struct *idle)
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{
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int ret = 0;
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pr_debug("Starting secondary CPU %d\n", cpu);
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if (per_cpu(cold_boot_done, cpu) == false) {
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if (of_board_is_sim()) {
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ret = msm_unclamp_secondary_arm_cpu_sim(cpu);
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if (ret)
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return ret;
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} else if (!of_board_is_rumi()) {
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ret = msm_unclamp_secondary_arm_cpu(cpu);
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if (ret)
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return ret;
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}
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per_cpu(cold_boot_done, cpu) = true;
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}
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return release_from_pen(cpu);
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}
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static int __cpuinit msm8976_boot_secondary(unsigned int cpu,
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struct task_struct *idle)
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{
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int ret = 0;
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u32 mpidr = cpu_logical_map(cpu);
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pr_debug("Starting secondary CPU %d\n", cpu);
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if (per_cpu(cold_boot_done, cpu) == false) {
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if (of_board_is_sim()) {
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ret = msm_unclamp_secondary_arm_cpu_sim(cpu);
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if (ret)
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return ret;
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} else if (!of_board_is_rumi()) {
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ret = msm8976_unclamp_secondary_arm_cpu(cpu);
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if (ret)
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return ret;
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}
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if (MPIDR_AFFINITY_LEVEL(mpidr, 1)) {
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ret = msm8976_cpu_ldo_config(cpu);
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if (ret)
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return ret;
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}
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per_cpu(cold_boot_done, cpu) = true;
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}
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return release_from_pen(cpu);
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}
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int __cpuinit arm_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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pr_debug("Starting secondary CPU %d\n", cpu);
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if (per_cpu(cold_boot_done, cpu) == false) {
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if (of_board_is_sim())
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release_secondary_sim(APCS_ALIAS0_BASE_ADDR, cpu);
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else if (!of_board_is_rumi())
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arm_release_secondary(APCS_ALIAS0_BASE_ADDR, cpu);
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per_cpu(cold_boot_done, cpu) = true;
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}
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return release_from_pen(cpu);
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}
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/*
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* Initialise the CPU possible map early - this describes the CPUs
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* which may be present or become present in the system.
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*/
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static void __init msm_smp_init_cpus(void)
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{
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unsigned int i, ncores = get_core_count();
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if (ncores > nr_cpu_ids) {
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pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
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ncores, nr_cpu_ids);
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ncores = nr_cpu_ids;
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}
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for (i = 0; i < ncores; i++)
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set_cpu_possible(i, true);
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}
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static void __init arm_smp_init_cpus(void)
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{
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unsigned int i, ncores;
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ncores = (__raw_readl(MSM_APCS_GCC_BASE + 0x30)) & 0xF;
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if (ncores > nr_cpu_ids) {
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pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
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ncores, nr_cpu_ids);
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ncores = nr_cpu_ids;
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}
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for (i = 0; i < ncores; i++)
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set_cpu_possible(i, true);
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}
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static int cold_boot_flags[] __initdata = {
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0,
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SCM_FLAG_COLDBOOT_CPU1,
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SCM_FLAG_COLDBOOT_CPU2,
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SCM_FLAG_COLDBOOT_CPU3,
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};
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static void __init msm_platform_smp_prepare_cpus_mc(unsigned int max_cpus)
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{
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int cpu, map;
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u32 aff0_mask = 0;
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u32 aff1_mask = 0;
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u32 aff2_mask = 0;
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for_each_present_cpu(cpu) {
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map = cpu_logical_map(cpu);
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aff0_mask |= BIT(MPIDR_AFFINITY_LEVEL(map, 0));
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aff1_mask |= BIT(MPIDR_AFFINITY_LEVEL(map, 1));
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aff2_mask |= BIT(MPIDR_AFFINITY_LEVEL(map, 2));
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}
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if (scm_set_boot_addr_mc(virt_to_phys(msm_secondary_startup),
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aff0_mask, aff1_mask, aff2_mask, SCM_FLAG_COLDBOOT_MC))
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pr_warn("Failed to set CPU boot address\n");
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/* Mark CPU0 cold boot flag as done */
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per_cpu(cold_boot_done, 0) = true;
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}
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static void __init msm_platform_smp_prepare_cpus(unsigned int max_cpus)
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{
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int cpu, map;
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unsigned int flags = 0;
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if (scm_is_mc_boot_available())
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return msm_platform_smp_prepare_cpus_mc(max_cpus);
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for_each_present_cpu(cpu) {
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map = cpu_logical_map(cpu);
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if (map >= ARRAY_SIZE(cold_boot_flags)) {
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set_cpu_present(cpu, false);
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__WARN();
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continue;
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}
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flags |= cold_boot_flags[map];
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}
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if (scm_set_boot_addr(virt_to_phys(msm_secondary_startup), flags))
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pr_warn("Failed to set CPU boot address\n");
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/* Mark CPU0 cold boot flag as done */
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per_cpu(cold_boot_done, 0) = true;
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}
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int msm_cpu_disable(unsigned int cpu)
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{
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return 0; /* support hotplugging any cpu */
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}
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struct smp_operations arm_smp_ops __initdata = {
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.smp_init_cpus = arm_smp_init_cpus,
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.smp_prepare_cpus = msm_platform_smp_prepare_cpus,
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.smp_secondary_init = msm_secondary_init,
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.smp_boot_secondary = arm_boot_secondary,
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#ifdef CONFIG_HOTPLUG
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.cpu_die = msm_cpu_die,
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.cpu_kill = msm_cpu_kill,
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#endif
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};
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struct smp_operations msm8916_smp_ops __initdata = {
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.smp_init_cpus = arm_smp_init_cpus,
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.smp_prepare_cpus = msm_platform_smp_prepare_cpus,
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.smp_secondary_init = msm_secondary_init,
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.smp_boot_secondary = msm8916_boot_secondary,
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#ifdef CONFIG_HOTPLUG
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.cpu_die = msm_cpu_die,
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.cpu_kill = msm_cpu_kill,
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.cpu_disable = msm_cpu_disable,
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#endif
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};
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struct smp_operations msm8976_smp_ops __initdata = {
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.smp_init_cpus = arm_smp_init_cpus,
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.smp_prepare_cpus = msm_platform_smp_prepare_cpus_mc,
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.smp_secondary_init = msm_secondary_init,
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.smp_boot_secondary = msm8976_boot_secondary,
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#ifdef CONFIG_HOTPLUG
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.cpu_die = msm_cpu_die,
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.cpu_kill = msm_cpu_kill,
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#endif
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};
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struct smp_operations msm8936_smp_ops __initdata = {
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.smp_init_cpus = arm_smp_init_cpus,
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.smp_prepare_cpus = msm_platform_smp_prepare_cpus,
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.smp_secondary_init = msm_secondary_init,
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.smp_boot_secondary = msm8936_boot_secondary,
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#ifdef CONFIG_HOTPLUG
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.cpu_die = msm_cpu_die,
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.cpu_kill = msm_cpu_kill,
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.cpu_disable = msm_cpu_disable,
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#endif
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};
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struct smp_operations msm8974_smp_ops __initdata = {
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.smp_init_cpus = msm_smp_init_cpus,
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.smp_prepare_cpus = msm_platform_smp_prepare_cpus,
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.smp_secondary_init = msm_secondary_init,
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.smp_boot_secondary = msm8974_boot_secondary,
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#ifdef CONFIG_HOTPLUG
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.cpu_die = msm_cpu_die,
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.cpu_kill = msm_cpu_kill,
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#endif
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};
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struct smp_operations msm8960_smp_ops __initdata = {
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.smp_init_cpus = msm_smp_init_cpus,
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.smp_prepare_cpus = msm_platform_smp_prepare_cpus,
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.smp_secondary_init = msm_secondary_init,
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|
.smp_boot_secondary = msm8960_boot_secondary,
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#ifdef CONFIG_HOTPLUG
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|
.cpu_die = msm_cpu_die,
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|
.cpu_kill = msm_cpu_kill,
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|
#endif
|
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};
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|
|
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struct smp_operations scorpion_smp_ops __initdata = {
|
|
.smp_init_cpus = msm_smp_init_cpus,
|
|
.smp_prepare_cpus = msm_platform_smp_prepare_cpus,
|
|
.smp_secondary_init = msm_secondary_init,
|
|
.smp_boot_secondary = scorpion_boot_secondary,
|
|
#ifdef CONFIG_HOTPLUG
|
|
.cpu_die = msm_cpu_die,
|
|
.cpu_kill = msm_cpu_kill,
|
|
#endif
|
|
};
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