697 lines
17 KiB
Plaintext
697 lines
17 KiB
Plaintext
/*
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* Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/pwm/pwm.h>
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/ {
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aliases {
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can0 = &can2;
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can1 = &can1;
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ethernet0 = &fec;
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lcdif_23bit_pins_a = &pinctrl_disp0_1;
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lcdif_24bit_pins_a = &pinctrl_disp0_2;
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pwm0 = &pwm1;
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pwm1 = &pwm2;
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reg_can_xcvr = ®_can_xcvr;
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stk5led = &user_led;
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usbotg = &usbotg;
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sdhc0 = &usdhc1;
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sdhc1 = &usdhc2;
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};
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memory {
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reg = <0 0>; /* will be filled by U-Boot */
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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mclk: clock@0 {
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compatible = "fixed-clock";
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reg = <0>;
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#clock-cells = <0>;
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clock-frequency = <27000000>;
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};
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};
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gpio-keys {
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compatible = "gpio-keys";
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power {
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label = "Power Button";
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gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
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linux,code = <KEY_POWER>;
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gpio-key,wakeup;
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};
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};
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leds {
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compatible = "gpio-leds";
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user_led: user {
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label = "Heartbeat";
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gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "heartbeat";
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};
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};
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regulators {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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reg_3v3_etn: regulator@0 {
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compatible = "regulator-fixed";
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reg = <0>;
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regulator-name = "3V3_ETN";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_etnphy_power>;
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gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_2v5: regulator@1 {
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compatible = "regulator-fixed";
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reg = <1>;
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regulator-name = "2V5";
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regulator-min-microvolt = <2500000>;
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regulator-max-microvolt = <2500000>;
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regulator-always-on;
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};
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reg_3v3: regulator@2 {
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compatible = "regulator-fixed";
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reg = <2>;
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regulator-name = "3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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reg_can_xcvr: regulator@3 {
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compatible = "regulator-fixed";
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reg = <3>;
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regulator-name = "CAN XCVR";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan_xcvr>;
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gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
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enable-active-low;
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};
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reg_lcd0_pwr: regulator@4 {
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compatible = "regulator-fixed";
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reg = <4>;
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regulator-name = "LCD0 POWER";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lcd0_pwr>;
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gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_lcd1_pwr: regulator@5 {
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compatible = "regulator-fixed";
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reg = <5>;
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regulator-name = "LCD1 POWER";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lcd1_pwr>;
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gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_usbh1_vbus: regulator@6 {
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compatible = "regulator-fixed";
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reg = <6>;
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regulator-name = "usbh1_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usbh1_vbus>;
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gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_usbotg_vbus: regulator@7 {
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compatible = "regulator-fixed";
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reg = <7>;
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regulator-name = "usbotg_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usbotg_vbus>;
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gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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sound {
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compatible = "karo,imx6qdl-tx6qdl-sgtl5000",
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"fsl,imx-audio-sgtl5000";
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model = "sgtl5000-audio";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_audmux>;
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ssi-controller = <&ssi1>;
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audio-codec = <&sgtl5000>;
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audio-routing =
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"MIC_IN", "Mic Jack",
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"Mic Jack", "Mic Bias",
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"Headphone Jack", "HP_OUT";
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mux-int-port = <1>;
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mux-ext-port = <5>;
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};
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};
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&audmux {
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status = "okay";
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};
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&can1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan1>;
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xceiver-supply = <®_can_xcvr>;
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status = "okay";
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};
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&can2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan2>;
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xceiver-supply = <®_can_xcvr>;
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status = "okay";
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};
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&ecspi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi1>;
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fsl,spi-num-chipselects = <2>;
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cs-gpios = <
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&gpio2 30 GPIO_ACTIVE_HIGH
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&gpio3 19 GPIO_ACTIVE_HIGH
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>;
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status = "okay";
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spidev0: spi@0 {
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compatible = "spidev";
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reg = <0>;
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spi-max-frequency = <54000000>;
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};
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spidev1: spi@1 {
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compatible = "spidev";
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reg = <1>;
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spi-max-frequency = <54000000>;
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};
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet>;
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phy-mode = "rmii";
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phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>;
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phy-supply = <®_3v3_etn>;
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status = "okay";
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};
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&gpmi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpmi_nand>;
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nand-on-flash-bbt;
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fsl,no-blockmark-swap;
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status = "okay";
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};
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&i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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clock-frequency = <400000>;
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status = "okay";
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ds1339: rtc@68 {
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compatible = "dallas,ds1339";
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reg = <0x68>;
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};
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};
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&i2c3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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clock-frequency = <400000>;
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status = "okay";
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sgtl5000: sgtl5000@0a {
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compatible = "fsl,sgtl5000";
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reg = <0x0a>;
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VDDA-supply = <®_2v5>;
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VDDIO-supply = <®_3v3>;
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clocks = <&mclk>;
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};
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polytouch: edt-ft5x06@38 {
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compatible = "edt,edt-ft5x06";
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reg = <0x38>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_edt_ft5x06>;
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interrupt-parent = <&gpio6>;
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interrupts = <15 0>;
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reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
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wake-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
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linux,wakeup;
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};
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touchscreen: tsc2007@48 {
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compatible = "ti,tsc2007";
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reg = <0x48>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_tsc2007>;
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interrupt-parent = <&gpio3>;
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interrupts = <26 0>;
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gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
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ti,x-plate-ohms = <660>;
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linux,wakeup;
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};
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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imx6qdl-tx6 {
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pinctrl_hog: hoggrp {
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fsl,pins = <
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MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1 /* LED */
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MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x1b0b1 /* ETN PHY RESET */
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MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b1 /* ETN PHY INT */
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MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* PWR BTN */
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>;
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};
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pinctrl_audmux: audmuxgrp {
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fsl,pins = <
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MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0 /* SSI1_RXD */
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MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 /* SSI1_TXD */
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MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 /* SSI1_CLK */
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MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 /* SSI1_FS */
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>;
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};
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pinctrl_disp0_1: disp0grp-1 {
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fsl,pins = <
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MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
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MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
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MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
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MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
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/* PAD DISP0_DAT0 is used for the Flexcan transceiver control */
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MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
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MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
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MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
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MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
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MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
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MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
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MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
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MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
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MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
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MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
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MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
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MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
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MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
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MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
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MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
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MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
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MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
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MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
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MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
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MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
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MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
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MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
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MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
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>;
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};
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pinctrl_disp0_2: disp0grp-2 {
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fsl,pins = <
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MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
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MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
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MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
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MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
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MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
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MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
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MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
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MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
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MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
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MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
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MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
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MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
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MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
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MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
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MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
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MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
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MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
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MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
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MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
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MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
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MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
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MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
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MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
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MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
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MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
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MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
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MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
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MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
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>;
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};
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pinctrl_ecspi1: ecspi1grp {
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fsl,pins = <
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MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x0b0b0
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MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x0b0b0
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MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x0b0b0
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MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x0b0b0
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MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x0b0b0 /* SPI CS0 */
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MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b0 /* SPI CS1 */
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>;
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};
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pinctrl_edt_ft5x06: edt-ft5x06grp {
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fsl,pins = <
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MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* Interrupt */
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MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /* Reset */
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MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 /* Wake */
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>;
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};
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pinctrl_enet: enetgrp {
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fsl,pins = <
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MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
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MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
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MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
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MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
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MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
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MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
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MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
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MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
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MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
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>;
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};
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pinctrl_etnphy_power: etnphy-pwrgrp {
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fsl,pins = <
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MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 /* ETN PHY POWER */
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>;
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};
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pinctrl_flexcan1: flexcan1grp {
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fsl,pins = <
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MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
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MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
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>;
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};
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|
|
pinctrl_flexcan2: flexcan2grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
|
|
MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
|
|
>;
|
|
};
|
|
|
|
pinctrl_flexcan_xcvr: flexcan-xcvrgrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b0b0 /* Flexcan XCVR enable */
|
|
>;
|
|
};
|
|
|
|
pinctrl_gpmi_nand: gpminandgrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1
|
|
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1
|
|
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1
|
|
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000
|
|
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1
|
|
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1
|
|
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1
|
|
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1
|
|
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1
|
|
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1
|
|
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1
|
|
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1
|
|
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1
|
|
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1
|
|
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c1: i2c1grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
|
|
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c3: i2c3grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
|
|
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_kpp: kppgrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_GPIO_9__KEY_COL6 0x1b0b1
|
|
MX6QDL_PAD_GPIO_4__KEY_COL7 0x1b0b1
|
|
MX6QDL_PAD_KEY_COL2__KEY_COL2 0x1b0b1
|
|
MX6QDL_PAD_KEY_COL3__KEY_COL3 0x1b0b1
|
|
MX6QDL_PAD_GPIO_2__KEY_ROW6 0x1b0b1
|
|
MX6QDL_PAD_GPIO_5__KEY_ROW7 0x1b0b1
|
|
MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b1
|
|
MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_lcd0_pwr: lcd0-pwrgrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b1 /* LCD Reset */
|
|
>;
|
|
};
|
|
|
|
pinctrl_lcd1_pwr: lcd1-pwrgrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b1 /* LCD Power Enable */
|
|
>;
|
|
};
|
|
|
|
pinctrl_pwm1: pwm1grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_pwm2: pwm2grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_tsc2007: tsc2007grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0 /* Interrupt */
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart1: uart1grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
|
|
MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart1_rtscts: uart1_rtsctsgrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x1b0b1
|
|
MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart2: uart2grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
|
|
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart2_rtscts: uart2_rtsctsgrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
|
|
MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart3: uart3grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
|
|
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart3_rtscts: uart3_rtsctsgrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x1b0b1
|
|
MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_usbh1_vbus: usbh1-vbusgrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 /* USBH1_VBUSEN */
|
|
>;
|
|
};
|
|
|
|
pinctrl_usbotg: usbotggrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x17059
|
|
>;
|
|
};
|
|
|
|
pinctrl_usbotg_vbus: usbotg-vbusgrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* USBOTG_VBUSEN */
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc1: usdhc1grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x070b1
|
|
MX6QDL_PAD_SD1_CLK__SD1_CLK 0x070b1
|
|
MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x070b1
|
|
MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x070b1
|
|
MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x070b1
|
|
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x070b1
|
|
MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x170b0 /* SD1 CD */
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2: usdhc2grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x070b1
|
|
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x070b1
|
|
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x070b1
|
|
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x070b1
|
|
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x070b1
|
|
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x070b1
|
|
MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x170b0 /* SD2 CD */
|
|
>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&kpp {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_kpp>;
|
|
/* sample keymap */
|
|
/* row/col 0,1 are mapped to KPP row/col 6,7 */
|
|
linux,keymap = <
|
|
MATRIX_KEY(6, 6, KEY_POWER) /* 0x06060074 */
|
|
MATRIX_KEY(6, 7, KEY_KP0) /* 0x06070052 */
|
|
MATRIX_KEY(6, 2, KEY_KP1) /* 0x0602004f */
|
|
MATRIX_KEY(6, 3, KEY_KP2) /* 0x06030050 */
|
|
MATRIX_KEY(7, 6, KEY_KP3) /* 0x07060051 */
|
|
MATRIX_KEY(7, 7, KEY_KP4) /* 0x0707004b */
|
|
MATRIX_KEY(7, 2, KEY_KP5) /* 0x0702004c */
|
|
MATRIX_KEY(7, 3, KEY_KP6) /* 0x0703004d */
|
|
MATRIX_KEY(2, 6, KEY_KP7) /* 0x02060047 */
|
|
MATRIX_KEY(2, 7, KEY_KP8) /* 0x02070048 */
|
|
MATRIX_KEY(2, 2, KEY_KP9) /* 0x02020049 */
|
|
>;
|
|
status = "okay";
|
|
};
|
|
|
|
&pwm1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_pwm1>;
|
|
#pwm-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
&pwm2 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_pwm2>;
|
|
#pwm-cells = <3>;
|
|
status = "okay";
|
|
};
|
|
|
|
&ssi1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&uart1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart1>;
|
|
status = "okay";
|
|
};
|
|
|
|
&uart2 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
|
|
status = "okay";
|
|
};
|
|
|
|
&uart3 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>;
|
|
status = "okay";
|
|
};
|
|
|
|
&usbh1 {
|
|
vbus-supply = <®_usbh1_vbus>;
|
|
dr_mode = "host";
|
|
disable-over-current;
|
|
status = "okay";
|
|
};
|
|
|
|
&usbotg {
|
|
vbus-supply = <®_usbotg_vbus>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_usbotg>;
|
|
dr_mode = "peripheral";
|
|
disable-over-current;
|
|
status = "okay";
|
|
};
|
|
|
|
&usdhc1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_usdhc1>;
|
|
bus-width = <4>;
|
|
no-1-8-v;
|
|
cd-gpios = <&gpio7 2 0>;
|
|
fsl,wp-controller;
|
|
status = "okay";
|
|
};
|
|
|
|
&usdhc2 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_usdhc2>;
|
|
bus-width = <4>;
|
|
no-1-8-v;
|
|
cd-gpios = <&gpio7 3 0>;
|
|
fsl,wp-controller;
|
|
status = "okay";
|
|
};
|