54 lines
1.9 KiB
Plaintext
54 lines
1.9 KiB
Plaintext
* MSM Serial UARTDM
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The MSM serial UARTDM hardware is designed for high-speed use cases where the
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transmit and/or receive channels can be offloaded to a dma-engine. From a
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software perspective it's mostly compatible with the MSM serial UART except
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that it supports reading and writing multiple characters at a time.
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Required properties:
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- compatible: Should contain at least "qcom,msm-uartdm".
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A more specific property should be specified as follows depending
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on the version:
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"qcom,msm-uartdm-v1.1"
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"qcom,msm-uartdm-v1.2"
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"qcom,msm-uartdm-v1.3"
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"qcom,msm-uartdm-v1.4"
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- reg: Should contain UART register locations and lengths. The first
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register shall specify the main control registers. An optional second
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register location shall specify the GSBI control region.
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"qcom,msm-uartdm-v1.3" is the only compatible value that might
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need the GSBI control region.
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- interrupts: Should contain UART interrupt.
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- clocks: Should contain the core clock and the AHB clock.
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- clock-names: Should be "core" for the core clock and "iface" for the
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AHB clock.
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Optional properties:
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- dmas: Should contain dma specifiers for transmit and receive channels
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- dma-names: Should contain "tx" for transmit and "rx" for receive channels
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Examples:
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A uartdm v1.4 device with dma capabilities.
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serial@f991e000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0xf991e000 0x1000>;
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interrupts = <0 108 0x0>;
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clocks = <&blsp1_uart2_apps_cxc>, <&blsp1_ahb_cxc>;
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clock-names = "core", "iface";
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dmas = <&dma0 0>, <&dma0 1>;
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dma-names = "tx", "rx";
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};
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A uartdm v1.3 device without dma capabilities and part of a GSBI complex.
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serial@19c40000 {
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compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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reg = <0x19c40000 0x1000>,
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<0x19c00000 0x1000>;
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interrupts = <0 195 0x0>;
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clocks = <&gsbi5_uart_cxc>, <&gsbi5_ahb_cxc>;
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clock-names = "core", "iface";
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};
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