184 lines
7.0 KiB
Plaintext
184 lines
7.0 KiB
Plaintext
Qualcomm QPNP power-on
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The qpnp-power-on is a driver which supports the power-on(PON)
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peripheral on Qualcomm PMICs. The supported functionality includes
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power on/off reason, key press/release detection, PMIC reset configurations
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and other PON specifc features. The PON module supports multiple physical
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power-on (KPDPWR_N, CBLPWR) and reset (KPDPWR_N, RESIN, KPDPWR+RESIN) sources.
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This peripheral is connected to the host processor via the SPMI interface.
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Required properties:
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- compatible: Must be "qcom,qpnp-power-on"
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- reg: Specifies the SPMI address and size for this PON (power-on) peripheral
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- interrupts: Specifies the interrupt associated with PON.
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- interrupt-names: Specify the interrupt names associated with interrupts. Must be
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one of "kpdpwr", "kpdpwr-bark", "resin", "resin-bark", "cblpwr",
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"kpdpwr-resin-bark". Bark interrupts are associated with system
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reset configuration to allow default reset configuration to be
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activated. If system reset configuration is not supported then
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bark interrupts are nops. Additionally, the "pmic-wd-bark"
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interrupt can be added if the system needs to handle PMIC
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watch dog barks.
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Optional properties:
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- qcom,pon-dbc-delay The debounce delay for the power-key interrupt
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specified in us. The value ranges from 2 seconds
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to 1/64 of a second. Possible values are -
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- 2, 1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64
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- Intermediate value is rounded down to the
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nearest valid value.
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- qcom,pon_1 ...pon_n These represent the child nodes which describe
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the properties (reset, key) for each of the pon
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reset source. All the child nodes are optional.
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If none of them is specified, the driver fails
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to register.
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- qcom,system-reset Specifies that this PON peripheral can be used
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to reset the system. This property can only be
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used by one device on the system. It is an error
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to include it more than once.
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- qcom,s3-debounce The debounce delay for stage3 reset trigger in
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secs. The values range from 0 to 128.
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- qcom,s3-src The source for stage 3 reset. It can be one of
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"kpdpwr", "resin", "kpdpwr-or-resin" or
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"kpdpwr-and-resin". The default value is
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"kpdpwr-and-resin".
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- qcom,uvlo-panic If this property is present, the device will set to panic during reboot if this reboot is due to under voltage lock out
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- qcom,clear-warm-reset Specifies that the WARM_RESET reason registers
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need to be cleared for this target. The property
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is used for the targets which have a hardware feature
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to catch resets which aren't triggered by the MSM.
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In such cases clearing WARM_REASON registers across
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MSM resets keeps the registers in good state.
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- qcom,secondary-pon-reset Boolean property which indicates that the PON
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peripheral is a secondary PON device which needs
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to be configured during reset in addition to the
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primary PON device that is configured for system
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reset through qcom,system-reset property.
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This should not be defined along with the
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qcom,system-reset property.
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- qcom,store-hard-reset-reason Boolean property which if set will store the hardware
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reset reason to SOFT_RB_SPARE register of the core PMIC
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PON peripheral.
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- qcom,warm-reset-poweroff-type Poweroff type required to be configured on
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PS_HOLD reset control register when the system
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goes for warm reset. If this property is not
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specified, then the default type, warm reset
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will be configured to PS_HOLD reset control
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register.
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- qcom,hard-reset-poweroff-type Same description as qcom,warm-reset-poweroff-type
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but this applies for the system hard reset case.
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- qcom,shutdown-poweroff-type Same description as qcom,warm-reset-poweroff-type
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but this applies for the system shutdown case.
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All the below properties are in the sub-node section (properties of the child
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node).
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Sub-nodes (if defined) should belong to either a PON configuration or a
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regulator configuration.
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Regulator sub-node required properties:
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- regulator-name Regulator name for the PON regulator that
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is being configured.
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- qcom,pon-spare-reg-addr Register offset from the base address of the PON
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peripheral that needs to be configured for the
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regulator being controlled.
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- qcom,pon-spare-reg-bit Bit position in the specified register that
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needs to be configured for the regulator being
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controlled.
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PON sub-node required properties:
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- qcom,pon-type The type of PON/RESET source. The driver
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currently supports KPDPWR(0), RESIN(1) and
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CBLPWR(2) pon/reset sources.
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PON sub-node optional properties:
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- qcom,pull-up The initial state of the reset pin under
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consideration.
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0 = No pull-up
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1 = pull-up enabled
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This property is set to '0' if not specified.
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- qcom,support-reset Indicates if this PON source supports
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reset functionality.
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0 = Not supported
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1 = Supported
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If this property is not defined, then do not modify S2 reset
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values.
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- qcom,use-bark Specify if this pon type needs to handle bark irq
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- linux,code The input key-code associated with the reset source.
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The reset source in its default configuration can be
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used to support standard keys.
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The below mentioned properties are required only when qcom,support-reset DT property is defined
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and is set to 1.
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- qcom,s1-timer The debounce timer for the BARK interrupt for
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that reset source. Value is specified in ms.
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Supported values are -
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- 0, 32, 56, 80, 128, 184, 272, 408, 608, 904
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1352, 2048, 3072, 4480, 6720, 10256
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- qcom,s2-timer The debounce timer for the S2 reset specified
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in ms. On the expiry of this timer, the PMIC
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executes the reset sequence. Supported values -
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- 0, 10, 50, 100, 250, 500, 1000, 2000
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- qcom,s2-type The type of reset associated with this source.
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The supported resets are -
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SOFT(0), WARM(1), SHUTDOWN(4), HARD(7)
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Example:
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qcom,power-on@800 {
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compatible = "qcom,qpnp-power-on";
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reg = <0x800 0x100>;
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interrupts = <0x0 0x8 0x0>,
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<0x0 0x8 0x1>,
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<0x0 0x8 0x4>,
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<0x0 0x8 0x5>;
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interrupt-names = "kpdpwr", "resin",
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"resin-bark", "kpdpwr-resin-bark";
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qcom,pon-dbc-delay = <15625>;
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qcom,system-reset;
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qcom,s3-debounce = <32>;
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qcom,s3-src = "resin";
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qcom,clear-warm-reset;
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qcom,store-hard-reset-reason;
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qcom,pon_1 {
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qcom,pon-type = <0>;
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qcom,pull-up = <1>;
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linux,code = <116>;
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};
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qcom,pon_2 {
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qcom,pon-type = <1>;
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qcom,support-reset = <1>;
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qcom,pull-up = <1>;
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qcom,s1-timer = <0>;
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qcom,s2-timer = <2000>;
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qcom,s2-type = <1>;
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linux,code = <114>;
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qcom,use-bark;
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};
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qcom,pon_3 {
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qcom,pon-type = <3>;
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qcom,support-reset = <1>;
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qcom,s1-timer = <6720>;
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qcom,s2-timer = <2000>;
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qcom,s2-type = <7>;
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qcom,pull-up = <1>;
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qcom,use-bark;
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};
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};
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qcom,power-on@800 {
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compatible = "qcom,qpnp-power-on";
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reg = <0x800 0x100>;
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qcom,secondary-pon-reset;
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qcom,hard-reset-poweroff-type = <PON_POWER_OFF_SHUTDOWN>;
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pon_perph_reg: qcom,pon_perph_reg {
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regulator-name = "pon_spare_reg";
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qcom,pon-spare-reg-addr = <0x8c>;
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qcom,pon-spare-reg-bit = <1>;
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};
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};
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