141 lines
5.3 KiB
Plaintext
141 lines
5.3 KiB
Plaintext
* Qualcomm MSM JPEG
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Required properties:
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- cell-index: jpeg hardware core index
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- compatible :
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- "qcom,jpeg"
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- "qcom,jpeg_dma"
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- reg : offset and length of the register set of jpeg device and vbif device
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for the jpeg operating in compatible mode.
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- reg-names : should specify relevant names to each reg property defined.
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- interrupts : should contain the jpeg interrupt.
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- interrupt-names : should specify relevant names to each interrupts
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property defined.
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- clock-names : names of clocks required for the device.
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- clocks : clocks required for the device.
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- qcom, clock-rates: rates of the required clocks.
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- vdd-supply: phandle to GDSC regulator controlling JPEG core.
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- mmagic-vdd-supply: phandle to GDSC regulator controlling mmagic.
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- camss-vdd-supply: phandle to GDSC regulator controlling camss.
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Optional properties:
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- qcom,vbif-reg-settings: relative address offsets and value pairs for VBIF registers.
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- qcom,qos-reg-settings: relative address offsets and value pairs for QoS registers.
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- qcom,prefetch-reg-settings: relative address offsets and value pairs for
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MMU prefetch registers.
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Example:
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qcom,jpeg@a1c000 {
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cell-index = <0>;
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compatible = "qcom,jpeg";
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reg = <0xa1c000 0x4000>,
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<0xa60000 0x3000>;
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reg-names = "jpeg";
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interrupts = <0 316 0>;
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interrupt-names = "jpeg";
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mmagic-vdd-supply = <&gdsc_mmagic_camss>;
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camss-vdd-supply = <&gdsc_camss_top>;
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vdd-supply = <&gdsc_jpeg>;
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qcom,vdd-names = "mmagic-vdd", "camss-vdd", "vdd";
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clock-names = "core_clk", "iface_clk", "bus_clk0",
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"camss_top_ahb_clk", "camss_ahb_clk", "smmu_jpeg_axi_clk",
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"mmss_mmagic_ahb_clk", "mmssnoc_axi_clk",
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"mmagic_camss_axi_clk";
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clocks = <&clock_mmss clk_camss_jpeg0_clk>,
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<&clock_mmss clk_camss_jpeg_ahb_clk>,
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<&clock_mmss clk_camss_jpeg_axi_clk>,
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<&clock_mmss clk_camss_top_ahb_clk>,
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<&clock_mmss clk_camss_ahb_clk>,
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<&clock_mmss clk_smmu_jpeg_axi_clk>,
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<&clock_mmss clk_mmss_mmagic_ahb_clk>,
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<&clock_gcc clk_mmssnoc_axi_clk>,
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<&clock_mmss clk_mmagic_camss_axi_clk>;
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qcom,clock-rates = <320000000 0 0 0 0 0 0 0 0>;
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qcom,vbif-reg-settings = <0x4 0x1>,
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<0xb0 0x00100010>,
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<0xc0 0x10001000>;
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qcom,qos-reg-settings = <0x28 0x00000008>;
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qcom,prefetch-reg-settings = <0x30c 0x1111>,
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<0x318 0x31>,
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<0x324 0x31>,
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<0x330 0x31>,
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<0x33c 0x0>;
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status = "ok";
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};
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qcom,jpeg@a24000 {
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cell-index = <2>;
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compatible = "qcom,jpeg";
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reg = <0xa24000 0x4000>,
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<0xa60000 0x3000>;
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reg-names = "jpeg";
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interrupts = <0 318 0>;
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interrupt-names = "jpeg";
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mmagic-vdd-supply = <&gdsc_mmagic_camss>;
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camss-vdd-supply = <&gdsc_camss_top>;
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vdd-supply = <&gdsc_jpeg>;
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qcom,vdd-names = "mmagic-vdd", "camss-vdd", "vdd";
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clock-names = "core_clk", "iface_clk", "bus_clk0",
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"camss_top_ahb_clk", "camss_ahb_clk", "smmu_jpeg_axi_clk",
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"mmss_mmagic_ahb_clk", "mmssnoc_axi_clk",
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"mmagic_camss_axi_clk";
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clocks = <&clock_mmss clk_camss_jpeg2_clk>,
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<&clock_mmss clk_camss_jpeg_ahb_clk>,
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<&clock_mmss clk_camss_jpeg_axi_clk>,
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<&clock_mmss clk_camss_top_ahb_clk>,
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<&clock_mmss clk_camss_ahb_clk>,
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<&clock_mmss clk_smmu_jpeg_axi_clk>,
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<&clock_mmss clk_mmss_mmagic_ahb_clk>,
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<&clock_gcc clk_mmssnoc_axi_clk>,
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<&clock_mmss clk_mmagic_camss_axi_clk>;
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qcom,clock-rates = <266670000 0 0 0 0 0 0 0 0>;
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qcom,vbif-reg-settings = <0x4 0x1>,
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<0xb0 0x00100010>,
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<0xc0 0x10001000>;
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qcom,qos-reg-settings = <0x28 0x00000008>;
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qcom,prefetch-reg-settings = <0x30c 0x1111>,
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<0x318 0x0>,
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<0x324 0x31>,
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<0x330 0x31>,
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<0x33c 0x31>;
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status = "ok";
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};
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qcom,jpeg@aa0000 {
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cell-index = <3>;
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compatible = "qcom,jpeg_dma";
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reg = <0xaa0000 0x4000>,
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<0xa60000 0x3000>;
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reg-names = "jpeg";
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interrupts = <0 304 0>;
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interrupt-names = "jpeg";
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mmagic-vdd-supply = <&gdsc_mmagic_camss>;
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camss-vdd-supply = <&gdsc_camss_top>;
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vdd-supply = <&gdsc_jpeg>;
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qcom,vdd-names = "mmagic-vdd", "camss-vdd", "vdd";
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clock-names = "core_clk", "iface_clk", "bus_clk0",
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"camss_top_ahb_clk", "camss_ahb_clk", "smmu_jpeg_axi_clk",
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"mmss_mmagic_ahb_clk", "mmssnoc_axi_clk",
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"mmagic_camss_axi_clk";
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clocks = <&clock_mmss clk_camss_jpeg_dma_clk>,
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<&clock_mmss clk_camss_jpeg_ahb_clk>,
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<&clock_mmss clk_camss_jpeg_axi_clk>,
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<&clock_mmss clk_camss_top_ahb_clk>,
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<&clock_mmss clk_camss_ahb_clk>,
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<&clock_mmss clk_smmu_jpeg_axi_clk>,
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<&clock_mmss clk_mmss_mmagic_ahb_clk>,
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<&clock_gcc clk_mmssnoc_axi_clk>,
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<&clock_mmss clk_mmagic_camss_axi_clk>;
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qcom,clock-rates = <266670000 0 0 0 0 0 0 0 0>;
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qcom,vbif-reg-settings = <0x4 0x1>,
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<0xb0 0x00100010>,
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<0xc0 0x10001000>;
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qcom,qos-reg-settings = <0x28 0x00000008>;
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qcom,prefetch-reg-settings = <0x18c 0x11>,
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<0x1a0 0x31>,
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<0x1b0 0x31>;
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status = "ok";
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};
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