66 lines
1.8 KiB
Plaintext
66 lines
1.8 KiB
Plaintext
Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream
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target devices. It can be configured to have one channel or two channels.
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If configured as two channels, one is to transmit to the device and another
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is to receive from the device.
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Required properties:
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- compatible: Should be "xlnx,axi-dma-1.00.a"
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- #dma-cells: Should be <1>, see "dmas" property below
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- reg: Should contain DMA registers location and length.
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- dma-channel child node: Should have atleast one channel and can have upto
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two channels per device. This node specifies the properties of each
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DMA channel (see child node properties below).
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Optional properties:
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- xlnx,include-sg: Tells whether configured for Scatter-mode in
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the hardware.
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Required child node properties:
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- compatible: It should be either "xlnx,axi-dma-mm2s-channel" or
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"xlnx,axi-dma-s2mm-channel".
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- interrupts: Should contain per channel DMA interrupts.
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- xlnx,datawidth: Should contain the stream data width, take values
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{32,64...1024}.
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Option child node properties:
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- xlnx,include-dre: Tells whether hardware is configured for Data
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Realignment Engine.
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Example:
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++++++++
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axi_dma_0: axidma@40400000 {
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compatible = "xlnx,axi-dma-1.00.a";
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#dma_cells = <1>;
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reg = < 0x40400000 0x10000 >;
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dma-channel@40400000 {
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compatible = "xlnx,axi-dma-mm2s-channel";
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interrupts = < 0 59 4 >;
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xlnx,datawidth = <0x40>;
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} ;
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dma-channel@40400030 {
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compatible = "xlnx,axi-dma-s2mm-channel";
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interrupts = < 0 58 4 >;
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xlnx,datawidth = <0x40>;
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} ;
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} ;
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* DMA client
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Required properties:
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- dmas: a list of <[DMA device phandle] [Channel ID]> pairs,
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where Channel ID is '0' for write/tx and '1' for read/rx
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channel.
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- dma-names: a list of DMA channel names, one per "dmas" entry
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Example:
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++++++++
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dmatest_0: dmatest@0 {
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compatible ="xlnx,axi-dma-test-1.00.a";
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dmas = <&axi_dma_0 0
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&axi_dma_0 1>;
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dma-names = "dma0", "dma1";
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} ;
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