52 lines
1.4 KiB
Plaintext
52 lines
1.4 KiB
Plaintext
Binding for a ST pll clock driver.
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This binding uses the common clock binding[1].
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Base address is located to the parent node. See clock binding[2]
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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[2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
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Required properties:
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- compatible : shall be:
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"st,clkgena-prediv-c65", "st,clkgena-prediv"
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"st,clkgena-prediv-c32", "st,clkgena-prediv"
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"st,clkgena-plls-c65"
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"st,plls-c32-a1x-0", "st,clkgen-plls-c32"
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"st,plls-c32-a1x-1", "st,clkgen-plls-c32"
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"st,stih415-plls-c32-a9", "st,clkgen-plls-c32"
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"st,stih415-plls-c32-ddr", "st,clkgen-plls-c32"
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"st,stih416-plls-c32-a9", "st,clkgen-plls-c32"
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"st,stih416-plls-c32-ddr", "st,clkgen-plls-c32"
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"st,stih407-plls-c32-a0", "st,clkgen-plls-c32"
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"st,stih407-plls-c32-a9", "st,clkgen-plls-c32"
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"st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32"
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"st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32"
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"st,stih415-gpu-pll-c32", "st,clkgengpu-pll-c32"
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"st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32"
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- #clock-cells : From common clock binding; shall be set to 1.
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- clocks : From common clock binding
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- clock-output-names : From common clock binding.
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Example:
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clockgen-a@fee62000 {
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reg = <0xfee62000 0xb48>;
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clk_s_a0_pll: clk-s-a0-pll {
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#clock-cells = <1>;
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compatible = "st,clkgena-plls-c65";
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clocks = <&clk_sysin>;
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clock-output-names = "clk-s-a0-pll0-hs",
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"clk-s-a0-pll0-ls",
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"clk-s-a0-pll1";
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};
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};
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