593 lines
14 KiB
C
593 lines
14 KiB
C
/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of The Linux Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <debug.h>
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#include <platform/iomap.h>
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#include <platform/irqs.h>
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#include <platform/gpio.h>
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#include <reg.h>
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#include <target.h>
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#include <platform.h>
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#include <dload_util.h>
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#include <uart_dm.h>
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#include <mmc.h>
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#include <spmi.h>
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#include <board.h>
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#include <smem.h>
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#include <baseband.h>
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#include <dev/keys.h>
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#include <pm8x41.h>
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#include <crypto5_wrapper.h>
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#include <hsusb.h>
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#include <clock.h>
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#include <partition_parser.h>
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#include <scm.h>
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#include <platform/clock.h>
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#include <platform/gpio.h>
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#include <platform/timer.h>
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#include <stdlib.h>
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#include <string.h>
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#include <ufs.h>
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#include <boot_device.h>
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#include <qmp_phy.h>
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#include <qusb2_phy.h>
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#include <rpm-smd.h>
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#include <sdhci_msm.h>
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#include <pm8x41_wled.h>
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#include <qpnp_led.h>
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#include "target/display.h"
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#define CE_INSTANCE 2
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#define CE_EE 1
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#define CE_FIFO_SIZE 64
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#define CE_READ_PIPE 3
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#define CE_WRITE_PIPE 2
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#define CE_READ_PIPE_LOCK_GRP 0
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#define CE_WRITE_PIPE_LOCK_GRP 0
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#define CE_ARRAY_SIZE 20
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#define PMIC_ARB_CHANNEL_NUM 0
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#define PMIC_ARB_OWNER_ID 0
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#define FASTBOOT_MODE 0x77665500
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#define PMIC_LED_SLAVE_ID 3
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#define DDR_CFG_DLY_VAL 0x80040870
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void target_crypto_init_params(void);
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static void set_sdc_power_ctrl(uint8_t slot);
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static uint32_t mmc_pwrctl_base[] =
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{ MSM_SDC1_BASE, MSM_SDC2_BASE };
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static uint32_t mmc_sdhci_base[] =
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{ MSM_SDC1_SDHCI_BASE, MSM_SDC2_SDHCI_BASE };
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static uint32_t mmc_sdc_pwrctl_irq[] =
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{ SDCC1_PWRCTL_IRQ, SDCC2_PWRCTL_IRQ };
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struct mmc_device *dev;
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struct ufs_dev ufs_device;
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extern void ulpi_write(unsigned val, unsigned reg);
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extern int platform_is_msm8994();
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void target_early_init(void)
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{
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#if WITH_DEBUG_UART
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uart_dm_init(2, 0, BLSP1_UART1_BASE);
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#endif
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}
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/* Return 1 if vol_up pressed */
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int target_volume_up()
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{
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uint8_t status = 0;
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struct pm8x41_gpio gpio;
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/* Configure the GPIO */
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gpio.direction = PM_GPIO_DIR_IN;
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gpio.function = 0;
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gpio.pull = PM_GPIO_PULL_UP_30;
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gpio.vin_sel = 2;
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pm8x41_gpio_config(3, &gpio);
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/* Wait for the pmic gpio config to take effect */
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thread_sleep(1);
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/* Get status of P_GPIO_5 */
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pm8x41_gpio_get(3, &status);
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return !status; /* active low */
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}
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/* Return 1 if vol_down pressed */
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uint32_t target_volume_down()
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{
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return pm8x41_resin_status();
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}
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static void target_keystatus()
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{
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keys_init();
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if(target_volume_down())
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keys_post_event(KEY_VOLUMEDOWN, 1);
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if(target_volume_up())
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keys_post_event(KEY_VOLUMEUP, 1);
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}
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void target_uninit(void)
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{
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if (platform_boot_dev_isemmc())
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{
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mmc_put_card_to_sleep(dev);
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/* Disable HC mode before jumping to kernel */
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sdhci_mode_disable(&dev->host);
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}
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if (crypto_initialized())
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{
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crypto_eng_cleanup();
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clock_ce_disable(CE_INSTANCE);
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}
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rpm_smd_uninit();
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}
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/* Do target specific usb initialization */
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void target_usb_init(void)
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{
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uint32_t val;
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if(board_hardware_id() == HW_PLATFORM_DRAGON)
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{
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/* Select the QUSB2 PHY */
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writel(0x1, USB2_PHY_SEL);
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qusb2_phy_reset();
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}
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/* Enable sess_vld */
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val = readl(USB_GENCONFIG_2) | GEN2_SESS_VLD_CTRL_EN;
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writel(val, USB_GENCONFIG_2);
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/* Enable external vbus configuration in the LINK */
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val = readl(USB_USBCMD);
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val |= SESS_VLD_CTRL;
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writel(val, USB_USBCMD);
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}
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void target_usb_stop(void)
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{
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}
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unsigned target_pause_for_battery_charge(void)
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{
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uint8_t pon_reason = pm8x41_get_pon_reason();
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uint8_t is_cold_boot = pm8x41_get_is_cold_boot();
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dprintf(INFO, "%s : pon_reason is %d cold_boot:%d\n", __func__,
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pon_reason, is_cold_boot);
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/* In case of fastboot reboot,adb reboot or if we see the power key
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* pressed we do not want go into charger mode.
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* fastboot reboot is warm boot with PON hard reset bit not set
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* adb reboot is a cold boot with PON hard reset bit set
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*/
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if (is_cold_boot &&
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(!(pon_reason & HARD_RST)) &&
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(!(pon_reason & KPDPWR_N)) &&
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((pon_reason & PON1)))
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return 1;
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else
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return 0;
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}
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static void set_sdc_power_ctrl(uint8_t slot)
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{
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uint32_t reg = 0;
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uint8_t clk;
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uint8_t cmd;
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uint8_t dat;
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if (slot == 0x1)
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{
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clk = TLMM_CUR_VAL_10MA;
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cmd = TLMM_CUR_VAL_8MA;
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dat = TLMM_CUR_VAL_8MA;
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reg = SDC1_HDRV_PULL_CTL;
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}
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else if (slot == 0x2)
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{
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clk = TLMM_CUR_VAL_16MA;
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cmd = TLMM_CUR_VAL_10MA;
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dat = TLMM_CUR_VAL_10MA;
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reg = SDC2_HDRV_PULL_CTL;
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}
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else
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{
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dprintf(CRITICAL, "Unsupported SDC slot passed\n");
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return;
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}
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/* Drive strength configs for sdc pins */
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struct tlmm_cfgs sdc1_hdrv_cfg[] =
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{
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{ SDC1_CLK_HDRV_CTL_OFF, clk, TLMM_HDRV_MASK, reg },
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{ SDC1_CMD_HDRV_CTL_OFF, cmd, TLMM_HDRV_MASK, reg },
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{ SDC1_DATA_HDRV_CTL_OFF, dat, TLMM_HDRV_MASK, reg },
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};
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/* Pull configs for sdc pins */
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struct tlmm_cfgs sdc1_pull_cfg[] =
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{
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{ SDC1_CLK_PULL_CTL_OFF, TLMM_NO_PULL, TLMM_PULL_MASK, reg },
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{ SDC1_CMD_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK, reg },
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{ SDC1_DATA_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK, reg },
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};
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struct tlmm_cfgs sdc1_rclk_cfg[] =
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{
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{ SDC1_RCLK_PULL_CTL_OFF, TLMM_PULL_DOWN, TLMM_PULL_MASK, reg },
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};
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/* Set the drive strength & pull control values */
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tlmm_set_hdrive_ctrl(sdc1_hdrv_cfg, ARRAY_SIZE(sdc1_hdrv_cfg));
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tlmm_set_pull_ctrl(sdc1_pull_cfg, ARRAY_SIZE(sdc1_pull_cfg));
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tlmm_set_pull_ctrl(sdc1_rclk_cfg, ARRAY_SIZE(sdc1_rclk_cfg));
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}
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void target_sdc_init()
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{
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struct mmc_config_data config = {0};
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config.bus_width = DATA_BUS_WIDTH_8BIT;
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config.max_clk_rate = MMC_CLK_192MHZ;
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/* Try slot 1*/
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config.slot = 1;
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config.sdhc_base = mmc_sdhci_base[config.slot - 1];
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config.pwrctl_base = mmc_pwrctl_base[config.slot - 1];
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config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
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config.hs400_support = 1;
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/* Set drive strength & pull ctrl values */
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set_sdc_power_ctrl(config.slot);
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if (!(dev = mmc_init(&config)))
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{
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/* Try slot 2 */
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config.slot = 2;
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config.max_clk_rate = MMC_CLK_200MHZ;
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config.sdhc_base = mmc_sdhci_base[config.slot - 1];
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config.pwrctl_base = mmc_pwrctl_base[config.slot - 1];
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config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
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/* Set drive strength & pull ctrl values */
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set_sdc_power_ctrl(config.slot);
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if (!(dev = mmc_init(&config)))
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{
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dprintf(CRITICAL, "mmc init failed!");
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ASSERT(0);
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}
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}
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}
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void *target_mmc_device()
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{
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if (platform_boot_dev_isemmc())
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return (void *) dev;
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else
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return (void *) &ufs_device;
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}
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void target_init(void)
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{
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dprintf(INFO, "target_init()\n");
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spmi_init(PMIC_ARB_CHANNEL_NUM, PMIC_ARB_OWNER_ID);
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target_keystatus();
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if (target_use_signed_kernel())
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target_crypto_init_params();
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platform_read_boot_config();
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#ifdef MMC_SDHCI_SUPPORT
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if (platform_boot_dev_isemmc())
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{
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target_sdc_init();
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}
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#endif
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#ifdef UFS_SUPPORT
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if(!platform_boot_dev_isemmc())
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{
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ufs_device.base = UFS_BASE;
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ufs_init(&ufs_device);
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}
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#endif
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/* Storage initialization is complete, read the partition table info */
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mmc_read_partition_table(0);
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rpm_smd_init();
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/* QPNP LED init for boot process notification */
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if (board_hardware_id() == HW_PLATFORM_LIQUID){
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pm8x41_wled_config_slave_id(PMIC_LED_SLAVE_ID);
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qpnp_led_init(QPNP_LED_BLUE, QPNP_LED_CTRL_BASE,
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QPNP_BLUE_LPG_CTRL_BASE);
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}
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}
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unsigned board_machtype(void)
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{
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return LINUX_MACHTYPE_UNKNOWN;
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}
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/* Detect the target type */
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void target_detect(struct board_data *board)
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{
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/* This is filled from board.c */
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}
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static uint8_t splash_override;
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/* Returns 1 if target supports continuous splash screen. */
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int target_cont_splash_screen()
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{
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uint8_t splash_screen = 0;
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if(!splash_override) {
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switch(board_hardware_id())
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{
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case HW_PLATFORM_SURF:
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case HW_PLATFORM_MTP:
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case HW_PLATFORM_FLUID:
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case HW_PLATFORM_LIQUID:
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dprintf(SPEW, "Target_cont_splash=1\n");
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splash_screen = 1;
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break;
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default:
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dprintf(SPEW, "Target_cont_splash=0\n");
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splash_screen = 0;
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}
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}
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return splash_screen;
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}
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void target_force_cont_splash_disable(uint8_t override)
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{
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splash_override = override;
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}
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/* Detect the modem type */
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void target_baseband_detect(struct board_data *board)
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{
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uint32_t platform;
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platform = board->platform;
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switch(platform) {
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case MSM8994:
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case MSM8992:
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board->baseband = BASEBAND_MSM;
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break;
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case APQ8094:
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case APQ8092:
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board->baseband = BASEBAND_APQ;
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break;
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default:
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dprintf(CRITICAL, "Platform type: %u is not supported\n",platform);
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ASSERT(0);
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};
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}
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unsigned target_baseband()
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{
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return board_baseband();
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}
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void target_serialno(unsigned char *buf)
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{
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uint32_t serialno;
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if (target_is_emmc_boot()) {
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if (platform_boot_dev_isemmc())
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serialno = mmc_get_psn();
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else
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serialno = board_chip_serial();
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snprintf((char *)buf, 13, "%x", serialno);
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}
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}
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unsigned check_reboot_mode(void)
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{
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uint32_t restart_reason = 0;
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uint32_t restart_reason_addr;
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if (platform_is_msm8994())
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restart_reason_addr = RESTART_REASON_ADDR;
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else
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restart_reason_addr = RESTART_REASON_ADDR2;
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/* Read reboot reason and scrub it */
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restart_reason = readl(restart_reason_addr);
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writel(0x00, restart_reason_addr);
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return restart_reason;
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}
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void reboot_device(unsigned reboot_reason)
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{
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uint8_t reset_type = 0;
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uint32_t restart_reason_addr;
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if (platform_is_msm8994())
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restart_reason_addr = RESTART_REASON_ADDR;
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else
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restart_reason_addr = RESTART_REASON_ADDR2;
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/* Write the reboot reason */
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writel(reboot_reason, restart_reason_addr);
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if(reboot_reason == FASTBOOT_MODE || reboot_reason == DLOAD)
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reset_type = PON_PSHOLD_WARM_RESET;
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else
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reset_type = PON_PSHOLD_HARD_RESET;
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pm8994_reset_configure(reset_type);
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/* Drop PS_HOLD for MSM */
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writel(0x00, MPM2_MPM_PS_HOLD);
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mdelay(5000);
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dprintf(CRITICAL, "Rebooting failed\n");
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}
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int emmc_recovery_init(void)
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{
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return _emmc_recovery_init();
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}
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target_usb_iface_t* target_usb30_init()
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{
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target_usb_iface_t *t_usb_iface;
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t_usb_iface = calloc(1, sizeof(target_usb_iface_t));
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ASSERT(t_usb_iface);
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t_usb_iface->mux_config = target_usb_phy_mux_configure;
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t_usb_iface->phy_init = usb30_qmp_phy_init;
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t_usb_iface->phy_reset = usb30_qmp_phy_reset;
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t_usb_iface->clock_init = clock_usb30_init;
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t_usb_iface->vbus_override = 1;
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return t_usb_iface;
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}
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/* identify the usb controller to be used for the target */
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const char * target_usb_controller()
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{
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if(board_hardware_id() == HW_PLATFORM_DRAGON)
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return "ci";
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return "dwc";
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}
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/* mux hs phy to route to dwc controller */
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static void phy_mux_configure_with_tcsr()
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{
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/* As per the hardware team, set the mux for snps controller */
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RMWREG32(TCSR_PHSS_USB2_PHY_SEL, 0x0, 0x1, 0x1);
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}
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/* configure hs phy mux if using dwc controller */
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void target_usb_phy_mux_configure(void)
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{
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if(!strcmp(target_usb_controller(), "dwc"))
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{
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phy_mux_configure_with_tcsr();
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}
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}
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uint32_t target_override_pll()
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{
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return 1;
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}
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/* Set up params for h/w CE. */
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void target_crypto_init_params()
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{
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struct crypto_init_params ce_params;
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/* Set up base addresses and instance. */
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ce_params.crypto_instance = CE_INSTANCE;
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ce_params.crypto_base = MSM_CE2_BASE;
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ce_params.bam_base = MSM_CE2_BAM_BASE;
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/* Set up BAM config. */
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ce_params.bam_ee = CE_EE;
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ce_params.pipes.read_pipe = CE_READ_PIPE;
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ce_params.pipes.write_pipe = CE_WRITE_PIPE;
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ce_params.pipes.read_pipe_grp = CE_READ_PIPE_LOCK_GRP;
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ce_params.pipes.write_pipe_grp = CE_WRITE_PIPE_LOCK_GRP;
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/* Assign buffer sizes. */
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ce_params.num_ce = CE_ARRAY_SIZE;
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ce_params.read_fifo_size = CE_FIFO_SIZE;
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ce_params.write_fifo_size = CE_FIFO_SIZE;
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|
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/* BAM is initialized by TZ for this platform.
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* Do not do it again as the initialization address space
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* is locked.
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*/
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ce_params.do_bam_init = 0;
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|
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crypto_init_params(&ce_params);
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|
}
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|
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crypto_engine_type board_ce_type(void)
|
|
{
|
|
return CRYPTO_ENGINE_TYPE_HW;
|
|
}
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|
|
|
void shutdown_device()
|
|
{
|
|
dprintf(CRITICAL, "Going down for shutdown.\n");
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|
|
|
/* Configure PMIC for shutdown. */
|
|
pm8994_reset_configure(PON_PSHOLD_SHUTDOWN);
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|
|
|
/* Drop PS_HOLD for MSM */
|
|
writel(0x00, MPM2_MPM_PS_HOLD);
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|
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mdelay(5000);
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|
|
|
dprintf(CRITICAL, "Shutdown failed\n");
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|
|
|
ASSERT(0);
|
|
}
|
|
|
|
uint32_t target_ddr_cfg_val()
|
|
{
|
|
return DDR_CFG_DLY_VAL;
|
|
}
|
|
|
|
int set_download_mode(enum dload_mode mode)
|
|
{
|
|
if (platform_is_msm8994())
|
|
dload_util_write_cookie(mode == NORMAL_DLOAD ?
|
|
DLOAD_MODE_ADDR : EMERGENCY_DLOAD_MODE_ADDR, mode);
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else
|
|
dload_util_write_cookie(mode == NORMAL_DLOAD ?
|
|
DLOAD_MODE_ADDR_V2 : EMERGENCY_DLOAD_MODE_ADDR_V2, mode);
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|
|
|
return 0;
|
|
}
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