877 lines
21 KiB
C
877 lines
21 KiB
C
/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of The Linux Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <assert.h>
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#include <reg.h>
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#include <err.h>
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#include <clock.h>
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#include <clock_pll.h>
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#include <clock_lib2.h>
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#include <platform/clock.h>
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#include <platform/iomap.h>
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/* Mux source select values */
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#define cxo_source_val 0
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#define gpll0_source_val 1
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#define gpll4_source_val 5
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#define cxo_mm_source_val 0
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#define mmpll0_mm_source_val 1
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#define mmpll1_mm_source_val 2
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#define mmpll3_mm_source_val 3
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#define gpll0_mm_source_val 5
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#define edppll_270_mm_source_val 4
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#define edppll_350_mm_source_val 4
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struct clk_freq_tbl rcg_dummy_freq = F_END;
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/* Clock Operations */
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static struct clk_ops clk_ops_branch =
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{
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.enable = clock_lib2_branch_clk_enable,
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.disable = clock_lib2_branch_clk_disable,
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.set_rate = clock_lib2_branch_set_rate,
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};
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static struct clk_ops clk_ops_rcg_mnd =
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{
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.enable = clock_lib2_rcg_enable,
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.set_rate = clock_lib2_rcg_set_rate,
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};
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static struct clk_ops clk_ops_rcg =
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{
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.enable = clock_lib2_rcg_enable,
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.set_rate = clock_lib2_rcg_set_rate,
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};
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static struct clk_ops clk_ops_cxo =
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{
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.enable = cxo_clk_enable,
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.disable = cxo_clk_disable,
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};
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static struct clk_ops clk_ops_pll_vote =
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{
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.enable = pll_vote_clk_enable,
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.disable = pll_vote_clk_disable,
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.auto_off = pll_vote_clk_disable,
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.is_enabled = pll_vote_clk_is_enabled,
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};
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static struct clk_ops clk_ops_vote =
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{
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.enable = clock_lib2_vote_clk_enable,
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.disable = clock_lib2_vote_clk_disable,
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};
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/* Clock Sources */
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static struct fixed_clk cxo_clk_src =
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{
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.c = {
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.rate = 19200000,
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.dbg_name = "cxo_clk_src",
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.ops = &clk_ops_cxo,
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},
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};
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static struct pll_vote_clk gpll0_clk_src =
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{
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.en_reg = (void *) APCS_GPLL_ENA_VOTE,
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.en_mask = BIT(0),
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.status_reg = (void *) GPLL0_STATUS,
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.status_mask = BIT(17),
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.parent = &cxo_clk_src.c,
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.c = {
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.rate = 600000000,
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.dbg_name = "gpll0_clk_src",
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.ops = &clk_ops_pll_vote,
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},
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};
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static struct pll_vote_clk gpll4_clk_src =
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{
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.en_reg = (void *) APCS_GPLL_ENA_VOTE,
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.en_mask = BIT(4),
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.status_reg = (void *) GPLL4_STATUS,
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.status_mask = BIT(17),
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.parent = &cxo_clk_src.c,
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.c = {
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.rate = 768000000,
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.dbg_name = "gpll4_clk_src",
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.ops = &clk_ops_pll_vote,
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},
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};
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/* SDCC Clocks */
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/* This table is for sdc1 apps clk only for MSM8974 PRO AC */
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static struct clk_freq_tbl ftbl_gcc_sdcc1_apps_clk_ac[] =
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{
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F( 144000, cxo, 16, 3, 25),
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F( 400000, cxo, 12, 1, 4),
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F( 20000000, gpll0, 15, 1, 2),
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F( 25000000, gpll0, 12, 1, 2),
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F( 50000000, gpll0, 12, 0, 0),
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F(100000000, gpll0, 6, 0, 0),
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F(192000000, gpll4, 4, 0, 0),
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F(384000000, gpll4, 2, 0, 0),
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F_END
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};
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/* This table is for
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* sdc[1-4] for all MSM8974 excluding MSM8974PROAC
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* sdc[2-4] for MSM8974PRO AC
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*/
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static struct clk_freq_tbl ftbl_gcc_sdcc1_4_apps_clk[] =
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{
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F( 144000, cxo, 16, 3, 25),
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F( 400000, cxo, 12, 1, 4),
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F( 20000000, gpll0, 15, 1, 2),
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F( 25000000, gpll0, 12, 1, 2),
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F( 50000000, gpll0, 12, 0, 0),
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F(100000000, gpll0, 6, 0, 0),
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F(200000000, gpll0, 3, 0, 0),
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F_END
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};
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static struct rcg_clk sdcc1_apps_clk_src =
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{
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.cmd_reg = (uint32_t *) SDCC1_CMD_RCGR,
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.cfg_reg = (uint32_t *) SDCC1_CFG_RCGR,
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.m_reg = (uint32_t *) SDCC1_M,
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.n_reg = (uint32_t *) SDCC1_N,
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.d_reg = (uint32_t *) SDCC1_D,
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.set_rate = clock_lib2_rcg_set_rate_mnd,
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.freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
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.current_freq = &rcg_dummy_freq,
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.c = {
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.dbg_name = "sdc1_clk",
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.ops = &clk_ops_rcg_mnd,
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},
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};
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static struct branch_clk gcc_sdcc1_apps_clk =
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{
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.cbcr_reg = (uint32_t *) SDCC1_APPS_CBCR,
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.parent = &sdcc1_apps_clk_src.c,
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.c = {
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.dbg_name = "gcc_sdcc1_apps_clk",
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.ops = &clk_ops_branch,
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},
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};
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static struct branch_clk gcc_sdcc1_ahb_clk =
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{
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.cbcr_reg = (uint32_t *) SDCC1_AHB_CBCR,
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.has_sibling = 1,
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.c = {
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.dbg_name = "gcc_sdcc1_ahb_clk",
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.ops = &clk_ops_branch,
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},
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};
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static struct branch_clk gcc_sdcc1_cdccal_sleep_clk =
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{
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.cbcr_reg = SDCC1_CDCCAL_SLEEP_CBCR,
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.has_sibling = 1,
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.c = {
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.dbg_name = "gcc_sdcc1_cdccal_sleep_clk",
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.ops = &clk_ops_branch,
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},
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};
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static struct branch_clk gcc_sdcc1_cdccal_ff_clk =
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{
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.cbcr_reg = SDCC1_CDCCAL_FF_CBCR,
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.has_sibling = 1,
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.c = {
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.dbg_name = "gcc_sdcc1_cdccal_ff_clk",
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.ops = &clk_ops_branch,
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},
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};
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static struct rcg_clk sdcc2_apps_clk_src =
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{
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.cmd_reg = (uint32_t *) SDCC2_CMD_RCGR,
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.cfg_reg = (uint32_t *) SDCC2_CFG_RCGR,
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.m_reg = (uint32_t *) SDCC2_M,
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.n_reg = (uint32_t *) SDCC2_N,
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.d_reg = (uint32_t *) SDCC2_D,
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.set_rate = clock_lib2_rcg_set_rate_mnd,
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.freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
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.current_freq = &rcg_dummy_freq,
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.c = {
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.dbg_name = "sdc2_clk",
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.ops = &clk_ops_rcg_mnd,
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},
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};
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static struct branch_clk gcc_sdcc2_apps_clk =
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{
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.cbcr_reg = (uint32_t *) SDCC2_APPS_CBCR,
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.parent = &sdcc2_apps_clk_src.c,
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.c = {
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.dbg_name = "gcc_sdcc2_apps_clk",
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.ops = &clk_ops_branch,
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},
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};
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static struct branch_clk gcc_sdcc2_ahb_clk =
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{
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.cbcr_reg = (uint32_t *) SDCC2_AHB_CBCR,
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.has_sibling = 1,
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.c = {
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.dbg_name = "gcc_sdcc2_ahb_clk",
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.ops = &clk_ops_branch,
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},
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};
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/* UART Clocks */
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static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] =
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{
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F( 3686400, gpll0, 1, 96, 15625),
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F( 7372800, gpll0, 1, 192, 15625),
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F(14745600, gpll0, 1, 384, 15625),
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F(16000000, gpll0, 5, 2, 15),
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F(19200000, cxo, 1, 0, 0),
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F(24000000, gpll0, 5, 1, 5),
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F(32000000, gpll0, 1, 4, 75),
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F(40000000, gpll0, 15, 0, 0),
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F(46400000, gpll0, 1, 29, 375),
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F(48000000, gpll0, 12.5, 0, 0),
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F(51200000, gpll0, 1, 32, 375),
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F(56000000, gpll0, 1, 7, 75),
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F(58982400, gpll0, 1, 1536, 15625),
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F(60000000, gpll0, 10, 0, 0),
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F_END
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};
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static struct rcg_clk blsp1_uart2_apps_clk_src =
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{
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.cmd_reg = (uint32_t *) BLSP1_UART2_APPS_CMD_RCGR,
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.cfg_reg = (uint32_t *) BLSP1_UART2_APPS_CFG_RCGR,
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.m_reg = (uint32_t *) BLSP1_UART2_APPS_M,
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.n_reg = (uint32_t *) BLSP1_UART2_APPS_N,
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.d_reg = (uint32_t *) BLSP1_UART2_APPS_D,
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.set_rate = clock_lib2_rcg_set_rate_mnd,
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.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
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.current_freq = &rcg_dummy_freq,
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.c = {
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.dbg_name = "blsp1_uart2_apps_clk",
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.ops = &clk_ops_rcg_mnd,
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},
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};
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static struct branch_clk gcc_blsp1_uart2_apps_clk =
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{
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.cbcr_reg = (uint32_t *) BLSP1_UART2_APPS_CBCR,
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.parent = &blsp1_uart2_apps_clk_src.c,
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.c = {
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.dbg_name = "gcc_blsp1_uart2_apps_clk",
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.ops = &clk_ops_branch,
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},
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};
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static struct vote_clk gcc_blsp1_ahb_clk = {
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.cbcr_reg = (uint32_t *) BLSP1_AHB_CBCR,
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.vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
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.en_mask = BIT(17),
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.c = {
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.dbg_name = "gcc_blsp1_ahb_clk",
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.ops = &clk_ops_vote,
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},
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};
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static struct vote_clk gcc_blsp2_ahb_clk = {
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.cbcr_reg = (uint32_t *) BLSP2_AHB_CBCR,
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.vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
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.en_mask = BIT(15),
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.c = {
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.dbg_name = "gcc_blsp2_ahb_clk",
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.ops = &clk_ops_vote,
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},
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};
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/* USB Clocks */
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static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] =
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{
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F(75000000, gpll0, 8, 0, 0),
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F_END
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};
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static struct rcg_clk usb_hs_system_clk_src =
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{
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.cmd_reg = (uint32_t *) USB_HS_SYSTEM_CMD_RCGR,
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.cfg_reg = (uint32_t *) USB_HS_SYSTEM_CFG_RCGR,
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.set_rate = clock_lib2_rcg_set_rate_hid,
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.freq_tbl = ftbl_gcc_usb_hs_system_clk,
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.current_freq = &rcg_dummy_freq,
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.c = {
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.dbg_name = "usb_hs_system_clk",
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.ops = &clk_ops_rcg,
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},
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};
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static struct branch_clk gcc_usb_hs_system_clk =
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{
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.cbcr_reg = (uint32_t *) USB_HS_SYSTEM_CBCR,
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.parent = &usb_hs_system_clk_src.c,
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.c = {
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.dbg_name = "gcc_usb_hs_system_clk",
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.ops = &clk_ops_branch,
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},
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};
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static struct branch_clk gcc_usb_hs_ahb_clk =
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{
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.cbcr_reg = (uint32_t *) USB_HS_AHB_CBCR,
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.has_sibling = 1,
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.c = {
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.dbg_name = "gcc_usb_hs_ahb_clk",
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.ops = &clk_ops_branch,
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},
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};
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/* CE Clocks */
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static struct clk_freq_tbl ftbl_gcc_ce2_clk[] = {
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F( 50000000, gpll0, 12, 0, 0),
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F(100000000, gpll0, 6, 0, 0),
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F_END
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};
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static struct rcg_clk ce2_clk_src = {
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.cmd_reg = (uint32_t *) GCC_CE2_CMD_RCGR,
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.cfg_reg = (uint32_t *) GCC_CE2_CFG_RCGR,
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.set_rate = clock_lib2_rcg_set_rate_hid,
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.freq_tbl = ftbl_gcc_ce2_clk,
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.current_freq = &rcg_dummy_freq,
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.c = {
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.dbg_name = "ce2_clk_src",
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.ops = &clk_ops_rcg,
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},
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};
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static struct vote_clk gcc_ce2_clk = {
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.cbcr_reg = (uint32_t *) GCC_CE2_CBCR,
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.vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
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.en_mask = BIT(2),
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.c = {
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.dbg_name = "gcc_ce2_clk",
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.ops = &clk_ops_vote,
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},
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};
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static struct vote_clk gcc_ce2_ahb_clk = {
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.cbcr_reg = (uint32_t *) GCC_CE2_AHB_CBCR,
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.vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
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.en_mask = BIT(0),
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.c = {
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.dbg_name = "gcc_ce2_ahb_clk",
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.ops = &clk_ops_vote,
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},
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};
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static struct vote_clk gcc_ce2_axi_clk = {
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.cbcr_reg = (uint32_t *) GCC_CE2_AXI_CBCR,
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.vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
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.en_mask = BIT(1),
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.c = {
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.dbg_name = "gcc_ce2_axi_clk",
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.ops = &clk_ops_vote,
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},
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};
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static struct clk_freq_tbl ftbl_gcc_ce1_clk[] = {
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F( 50000000, gpll0, 12, 0, 0),
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F(100000000, gpll0, 6, 0, 0),
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F_END
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};
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static struct rcg_clk ce1_clk_src = {
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.cmd_reg = (uint32_t *) GCC_CE1_CMD_RCGR,
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.cfg_reg = (uint32_t *) GCC_CE1_CFG_RCGR,
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.set_rate = clock_lib2_rcg_set_rate_hid,
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.freq_tbl = ftbl_gcc_ce1_clk,
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.current_freq = &rcg_dummy_freq,
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.c = {
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.dbg_name = "ce1_clk_src",
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.ops = &clk_ops_rcg,
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},
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};
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static struct vote_clk gcc_ce1_clk = {
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.cbcr_reg = (uint32_t *) GCC_CE1_CBCR,
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.vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
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.en_mask = BIT(5),
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.c = {
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.dbg_name = "gcc_ce1_clk",
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.ops = &clk_ops_vote,
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},
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};
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static struct vote_clk gcc_ce1_ahb_clk = {
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.cbcr_reg = (uint32_t *) GCC_CE1_AHB_CBCR,
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.vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
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.en_mask = BIT(3),
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.c = {
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.dbg_name = "gcc_ce1_ahb_clk",
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.ops = &clk_ops_vote,
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},
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};
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static struct vote_clk gcc_ce1_axi_clk = {
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.cbcr_reg = (uint32_t *) GCC_CE1_AXI_CBCR,
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.vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
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.en_mask = BIT(4),
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.c = {
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.dbg_name = "gcc_ce1_axi_clk",
|
|
.ops = &clk_ops_vote,
|
|
},
|
|
};
|
|
|
|
|
|
struct branch_clk gcc_blsp2_qup5_i2c_apps_clk = {
|
|
.cbcr_reg = BLSP2_QUP5_I2C_APPS_CBCR,
|
|
.parent = &cxo_clk_src.c,
|
|
|
|
.c = {
|
|
.dbg_name = "gcc_blsp2_qup5_i2c_apps_clk",
|
|
.ops = &clk_ops_branch,
|
|
},
|
|
};
|
|
|
|
/* Display clocks */
|
|
static struct clk_freq_tbl ftbl_mdss_esc0_1_clk[] = {
|
|
F_MM(19200000, cxo, 1, 0, 0),
|
|
F_END
|
|
};
|
|
|
|
static struct clk_freq_tbl ftbl_mdss_esc1_1_clk[] = {
|
|
F_MM(19200000, cxo, 1, 0, 0),
|
|
F_END
|
|
};
|
|
|
|
static struct clk_freq_tbl ftbl_mmss_axi_clk[] = {
|
|
F_MM(19200000, cxo, 1, 0, 0),
|
|
F_MM(100000000, gpll0, 6, 0, 0),
|
|
F_END
|
|
};
|
|
|
|
static struct clk_freq_tbl ftbl_mdp_clk[] = {
|
|
F_MM( 75000000, gpll0, 8, 0, 0),
|
|
F_MM( 240000000, gpll0, 2.5, 0, 0),
|
|
F_END
|
|
};
|
|
|
|
static struct rcg_clk dsi_esc0_clk_src = {
|
|
.cmd_reg = (uint32_t *) DSI_ESC0_CMD_RCGR,
|
|
.cfg_reg = (uint32_t *) DSI_ESC0_CFG_RCGR,
|
|
.set_rate = clock_lib2_rcg_set_rate_hid,
|
|
.freq_tbl = ftbl_mdss_esc0_1_clk,
|
|
|
|
.c = {
|
|
.dbg_name = "dsi_esc0_clk_src",
|
|
.ops = &clk_ops_rcg,
|
|
},
|
|
};
|
|
|
|
static struct rcg_clk dsi_esc1_clk_src = {
|
|
.cmd_reg = (uint32_t *) DSI_ESC1_CMD_RCGR,
|
|
.cfg_reg = (uint32_t *) DSI_ESC1_CFG_RCGR,
|
|
.set_rate = clock_lib2_rcg_set_rate_hid,
|
|
.freq_tbl = ftbl_mdss_esc1_1_clk,
|
|
|
|
.c = {
|
|
.dbg_name = "dsi_esc1_clk_src",
|
|
.ops = &clk_ops_rcg,
|
|
},
|
|
};
|
|
|
|
static struct clk_freq_tbl ftbl_mdss_vsync_clk[] = {
|
|
F_MM(19200000, cxo, 1, 0, 0),
|
|
F_END
|
|
};
|
|
|
|
static struct rcg_clk vsync_clk_src = {
|
|
.cmd_reg = (uint32_t *) VSYNC_CMD_RCGR,
|
|
.cfg_reg = (uint32_t *) VSYNC_CFG_RCGR,
|
|
.set_rate = clock_lib2_rcg_set_rate_hid,
|
|
.freq_tbl = ftbl_mdss_vsync_clk,
|
|
|
|
.c = {
|
|
.dbg_name = "vsync_clk_src",
|
|
.ops = &clk_ops_rcg,
|
|
},
|
|
};
|
|
|
|
static struct rcg_clk mdp_axi_clk_src = {
|
|
.cmd_reg = (uint32_t *) MDP_AXI_CMD_RCGR,
|
|
.cfg_reg = (uint32_t *) MDP_AXI_CFG_RCGR,
|
|
.set_rate = clock_lib2_rcg_set_rate_hid,
|
|
.freq_tbl = ftbl_mmss_axi_clk,
|
|
|
|
.c = {
|
|
.dbg_name = "mdp_axi_clk_src",
|
|
.ops = &clk_ops_rcg,
|
|
},
|
|
};
|
|
|
|
static struct branch_clk mdss_esc0_clk = {
|
|
.cbcr_reg = (uint32_t *) DSI_ESC0_CBCR,
|
|
.parent = &dsi_esc0_clk_src.c,
|
|
.has_sibling = 0,
|
|
|
|
.c = {
|
|
.dbg_name = "mdss_esc0_clk",
|
|
.ops = &clk_ops_branch,
|
|
},
|
|
};
|
|
|
|
static struct branch_clk mdss_esc1_clk = {
|
|
.cbcr_reg = (uint32_t *) DSI_ESC1_CBCR,
|
|
.parent = &dsi_esc1_clk_src.c,
|
|
.has_sibling = 0,
|
|
|
|
.c = {
|
|
.dbg_name = "mdss_esc1_clk",
|
|
.ops = &clk_ops_branch,
|
|
},
|
|
};
|
|
|
|
static struct branch_clk mdss_axi_clk = {
|
|
.cbcr_reg = (uint32_t *) MDP_AXI_CBCR,
|
|
.parent = &mdp_axi_clk_src.c,
|
|
.has_sibling = 0,
|
|
|
|
.c = {
|
|
.dbg_name = "mdss_axi_clk",
|
|
.ops = &clk_ops_branch,
|
|
},
|
|
};
|
|
|
|
static struct branch_clk mmss_mmssnoc_axi_clk = {
|
|
.cbcr_reg = (uint32_t *) MMSS_MMSSNOC_AXI_CBCR,
|
|
.parent = &mdp_axi_clk_src.c,
|
|
.has_sibling = 0,
|
|
|
|
.c = {
|
|
.dbg_name = "mmss_mmssnoc_axi_clk",
|
|
.ops = &clk_ops_branch,
|
|
},
|
|
};
|
|
|
|
static struct branch_clk mmss_s0_axi_clk = {
|
|
.cbcr_reg = (uint32_t *) MMSS_S0_AXI_CBCR,
|
|
.parent = &mdp_axi_clk_src.c,
|
|
.has_sibling = 0,
|
|
|
|
.c = {
|
|
.dbg_name = "mmss_s0_axi_clk",
|
|
.ops = &clk_ops_branch,
|
|
},
|
|
};
|
|
|
|
static struct branch_clk mdp_ahb_clk = {
|
|
.cbcr_reg = (uint32_t *) MDP_AHB_CBCR,
|
|
.has_sibling = 1,
|
|
|
|
.c = {
|
|
.dbg_name = "mdp_ahb_clk",
|
|
.ops = &clk_ops_branch,
|
|
},
|
|
};
|
|
|
|
static struct rcg_clk mdss_mdp_clk_src = {
|
|
.cmd_reg = (uint32_t *) MDP_CMD_RCGR,
|
|
.cfg_reg = (uint32_t *) MDP_CFG_RCGR,
|
|
.set_rate = clock_lib2_rcg_set_rate_hid,
|
|
.freq_tbl = ftbl_mdp_clk,
|
|
.current_freq = &rcg_dummy_freq,
|
|
|
|
.c = {
|
|
.dbg_name = "mdss_mdp_clk_src",
|
|
.ops = &clk_ops_rcg,
|
|
},
|
|
};
|
|
|
|
static struct branch_clk mdss_mdp_clk = {
|
|
.cbcr_reg = (uint32_t *) MDP_CBCR,
|
|
.parent = &mdss_mdp_clk_src.c,
|
|
.has_sibling = 1,
|
|
|
|
.c = {
|
|
.dbg_name = "mdss_mdp_clk",
|
|
.ops = &clk_ops_branch,
|
|
},
|
|
};
|
|
|
|
static struct branch_clk mdss_mdp_lut_clk = {
|
|
.cbcr_reg = MDP_LUT_CBCR,
|
|
.parent = &mdss_mdp_clk_src.c,
|
|
.has_sibling = 1,
|
|
|
|
.c = {
|
|
.dbg_name = "mdss_mdp_lut_clk",
|
|
.ops = &clk_ops_branch,
|
|
},
|
|
};
|
|
|
|
static struct branch_clk mdss_vsync_clk = {
|
|
.cbcr_reg = MDSS_VSYNC_CBCR,
|
|
.parent = &vsync_clk_src.c,
|
|
.has_sibling = 0,
|
|
|
|
.c = {
|
|
.dbg_name = "mdss_vsync_clk",
|
|
.ops = &clk_ops_branch,
|
|
},
|
|
};
|
|
|
|
static struct clk_freq_tbl ftbl_mdss_edpaux_clk[] = {
|
|
F_MM(19200000, cxo, 1, 0, 0),
|
|
F_END
|
|
};
|
|
|
|
static struct rcg_clk edpaux_clk_src = {
|
|
.cmd_reg = (uint32_t *) EDPAUX_CMD_RCGR,
|
|
.set_rate = clock_lib2_rcg_set_rate_hid,
|
|
.freq_tbl = ftbl_mdss_edpaux_clk,
|
|
|
|
.c = {
|
|
.dbg_name = "edpaux_clk_src",
|
|
.ops = &clk_ops_rcg,
|
|
},
|
|
};
|
|
|
|
static struct branch_clk mdss_edpaux_clk = {
|
|
.cbcr_reg = MDSS_EDPAUX_CBCR,
|
|
.parent = &edpaux_clk_src.c,
|
|
.has_sibling = 0,
|
|
|
|
.c = {
|
|
.dbg_name = "mdss_edpaux_clk",
|
|
.ops = &clk_ops_branch,
|
|
},
|
|
};
|
|
|
|
static struct clk_freq_tbl ftbl_mdss_edplink_clk[] = {
|
|
F_MDSS(162000000, edppll_270, 2, 0, 0),
|
|
F_MDSS(270000000, edppll_270, 11, 0, 0),
|
|
F_END
|
|
};
|
|
|
|
static struct rcg_clk edplink_clk_src = {
|
|
.cmd_reg = (uint32_t *)EDPLINK_CMD_RCGR,
|
|
.set_rate = clock_lib2_rcg_set_rate_hid,
|
|
.freq_tbl = ftbl_mdss_edplink_clk,
|
|
.current_freq = &rcg_dummy_freq,
|
|
.c = {
|
|
.dbg_name = "edplink_clk_src",
|
|
.ops = &clk_ops_rcg,
|
|
},
|
|
};
|
|
|
|
static struct clk_freq_tbl ftbl_mdss_edppixel_clk[] = {
|
|
F_MDSS(138500000, edppll_350, 2, 0, 0),
|
|
F_MDSS(350000000, edppll_350, 11, 0, 0),
|
|
F_END
|
|
};
|
|
|
|
static struct rcg_clk edppixel_clk_src = {
|
|
.cmd_reg = (uint32_t *)EDPPIXEL_CMD_RCGR,
|
|
.set_rate = clock_lib2_rcg_set_rate_mnd,
|
|
.freq_tbl = ftbl_mdss_edppixel_clk,
|
|
.current_freq = &rcg_dummy_freq,
|
|
.c = {
|
|
.dbg_name = "edppixel_clk_src",
|
|
.ops = &clk_ops_rcg_mnd,
|
|
},
|
|
};
|
|
|
|
static struct branch_clk mdss_edplink_clk = {
|
|
.cbcr_reg = (uint32_t *)MDSS_EDPLINK_CBCR,
|
|
.has_sibling = 0,
|
|
.parent = &edplink_clk_src.c,
|
|
.c = {
|
|
.dbg_name = "mdss_edplink_clk",
|
|
.ops = &clk_ops_branch,
|
|
},
|
|
};
|
|
|
|
static struct branch_clk mdss_edppixel_clk = {
|
|
.cbcr_reg = (uint32_t *)MDSS_EDPPIXEL_CBCR,
|
|
.has_sibling = 0,
|
|
.parent = &edppixel_clk_src.c,
|
|
.c = {
|
|
.dbg_name = "mdss_edppixel_clk",
|
|
.ops = &clk_ops_branch,
|
|
},
|
|
};
|
|
|
|
/* USB 3.0 Clocks */
|
|
static struct clk_freq_tbl ftbl_gcc_usb30_master_clk[] =
|
|
{
|
|
F(125000000, gpll0, 1, 5, 24),
|
|
F_END
|
|
};
|
|
|
|
static struct rcg_clk usb30_master_clk_src =
|
|
{
|
|
.cmd_reg = (uint32_t *) GCC_USB30_MASTER_CMD_RCGR,
|
|
.cfg_reg = (uint32_t *) GCC_USB30_MASTER_CFG_RCGR,
|
|
.m_reg = (uint32_t *) GCC_USB30_MASTER_M,
|
|
.n_reg = (uint32_t *) GCC_USB30_MASTER_N,
|
|
.d_reg = (uint32_t *) GCC_USB30_MASTER_D,
|
|
|
|
.set_rate = clock_lib2_rcg_set_rate_mnd,
|
|
.freq_tbl = ftbl_gcc_usb30_master_clk,
|
|
.current_freq = &rcg_dummy_freq,
|
|
|
|
.c = {
|
|
.dbg_name = "usb30_master_clk_src",
|
|
.ops = &clk_ops_rcg,
|
|
},
|
|
};
|
|
|
|
|
|
static struct branch_clk gcc_usb30_master_clk =
|
|
{
|
|
.cbcr_reg = (uint32_t *) GCC_USB30_MASTER_CBCR,
|
|
.parent = &usb30_master_clk_src.c,
|
|
|
|
.c = {
|
|
.dbg_name = "gcc_usb30_master_clk",
|
|
.ops = &clk_ops_branch,
|
|
},
|
|
};
|
|
|
|
static struct branch_clk gcc_sys_noc_usb30_axi_clk =
|
|
{
|
|
.cbcr_reg = (uint32_t *) SYS_NOC_USB3_AXI_CBCR,
|
|
.has_sibling = 1,
|
|
|
|
.c = {
|
|
.dbg_name = "gcc_sys_noc_usb3_axi_clk",
|
|
.ops = &clk_ops_branch,
|
|
},
|
|
};
|
|
|
|
/* Clock lookup table */
|
|
static struct clk_lookup msm_clocks_8974[] =
|
|
{
|
|
CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c),
|
|
CLK_LOOKUP("sdc1_core_clk", gcc_sdcc1_apps_clk.c),
|
|
|
|
CLK_LOOKUP("gcc_sdcc1_cdccal_sleep_clk", gcc_sdcc1_cdccal_sleep_clk.c),
|
|
CLK_LOOKUP("gcc_sdcc1_cdccal_ff_clk", gcc_sdcc1_cdccal_ff_clk.c),
|
|
|
|
CLK_LOOKUP("sdc2_iface_clk", gcc_sdcc2_ahb_clk.c),
|
|
CLK_LOOKUP("sdc2_core_clk", gcc_sdcc2_apps_clk.c),
|
|
|
|
CLK_LOOKUP("uart2_iface_clk", gcc_blsp1_ahb_clk.c),
|
|
CLK_LOOKUP("uart2_core_clk", gcc_blsp1_uart2_apps_clk.c),
|
|
|
|
CLK_LOOKUP("usb_iface_clk", gcc_usb_hs_ahb_clk.c),
|
|
CLK_LOOKUP("usb_core_clk", gcc_usb_hs_system_clk.c),
|
|
|
|
CLK_LOOKUP("ce2_ahb_clk", gcc_ce2_ahb_clk.c),
|
|
CLK_LOOKUP("ce2_axi_clk", gcc_ce2_axi_clk.c),
|
|
CLK_LOOKUP("ce2_core_clk", gcc_ce2_clk.c),
|
|
CLK_LOOKUP("ce2_src_clk", ce2_clk_src.c),
|
|
|
|
CLK_LOOKUP("ce1_ahb_clk", gcc_ce1_ahb_clk.c),
|
|
CLK_LOOKUP("ce1_axi_clk", gcc_ce1_axi_clk.c),
|
|
CLK_LOOKUP("ce1_core_clk", gcc_ce1_clk.c),
|
|
CLK_LOOKUP("ce1_src_clk", ce1_clk_src.c),
|
|
|
|
|
|
CLK_LOOKUP("blsp2_ahb_clk", gcc_blsp2_ahb_clk.c),
|
|
CLK_LOOKUP("blsp2_qup5_i2c_apps_clk", gcc_blsp2_qup5_i2c_apps_clk.c),
|
|
|
|
CLK_LOOKUP("mdp_ahb_clk", mdp_ahb_clk.c),
|
|
CLK_LOOKUP("mdss_esc0_clk", mdss_esc0_clk.c),
|
|
CLK_LOOKUP("mdss_esc1_clk", mdss_esc1_clk.c),
|
|
CLK_LOOKUP("mdss_axi_clk", mdss_axi_clk.c),
|
|
CLK_LOOKUP("mmss_mmssnoc_axi_clk", mmss_mmssnoc_axi_clk.c),
|
|
CLK_LOOKUP("mmss_s0_axi_clk", mmss_s0_axi_clk.c),
|
|
CLK_LOOKUP("mdss_vsync_clk", mdss_vsync_clk.c),
|
|
CLK_LOOKUP("mdss_mdp_clk_src", mdss_mdp_clk_src.c),
|
|
CLK_LOOKUP("mdss_mdp_clk", mdss_mdp_clk.c),
|
|
CLK_LOOKUP("mdss_mdp_lut_clk", mdss_mdp_lut_clk.c),
|
|
|
|
CLK_LOOKUP("edp_pixel_clk", mdss_edppixel_clk.c),
|
|
CLK_LOOKUP("edp_link_clk", mdss_edplink_clk.c),
|
|
CLK_LOOKUP("edp_aux_clk", mdss_edpaux_clk.c),
|
|
|
|
/* USB 3.0 */
|
|
CLK_LOOKUP("usb30_iface_clk", gcc_sys_noc_usb30_axi_clk.c),
|
|
CLK_LOOKUP("usb30_master_clk", gcc_usb30_master_clk.c),
|
|
};
|
|
|
|
void msm8974_ac_clock_override()
|
|
{
|
|
sdcc1_apps_clk_src.freq_tbl = ftbl_gcc_sdcc1_apps_clk_ac;
|
|
}
|
|
|
|
void platform_clock_init(void)
|
|
{
|
|
if (platform_is_8974ac())
|
|
msm8974_ac_clock_override();
|
|
clk_init(msm_clocks_8974, ARRAY_SIZE(msm_clocks_8974));
|
|
}
|