329 lines
12 KiB
C
329 lines
12 KiB
C
/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above
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copyright notice, this list of conditions and the following
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disclaimer in the documentation and/or other materials provided
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with the distribution.
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* Neither the name of The Linux Foundation nor the names of its
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <debug.h>
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#include <sys/types.h>
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#include <compiler.h>
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#include <arch.h>
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#include <arch/arm.h>
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#include <arch/ops.h>
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#include <arch/defines.h>
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#include <arch/arm/mmu.h>
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#include <mmu.h>
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#include <platform.h>
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#include <stdlib.h>
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#if ARM_WITH_MMU
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#define LPAE_SIZE (1ULL << 40)
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#define LPAE_MASK (LPAE_SIZE - 1)
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#define L1_PT_INDEX 0x7FC0000000
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#define PT_TABLE_DESC_BIT 0x2
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#define SIZE_1GB (0x400000000UL)
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#define SIZE_2MB (0x200000)
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#define MMU_L2_PT_SIZE 512
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#define MMU_PT_BLOCK_DESCRIPTOR 0x1
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#define MMU_PT_TABLE_DESCRIPTOR 0x3
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#define MMU_AP_FLAG (0x1 << 10)
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#define L2_PT_MASK 0xFFFFE00000
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#define L2_INDEX_MASK 0x3FE00000
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uint64_t mmu_l1_pagetable[ROUNDUP(L1_PT_SZ, CACHE_LINE)] __attribute__ ((aligned(4096))); /* Max is 8 */
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uint64_t mmu_l2_pagetable[ROUNDUP(L2_PT_SZ*MMU_L2_PT_SIZE, CACHE_LINE)] __attribute__ ((aligned(4096))); /* Macro from target code * 512 */
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uint64_t avail_l2_pt = L2_PT_SZ;
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uint64_t *empty_l2_pt = mmu_l2_pagetable;
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/************************************************************/
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/* MAP 2MB granules in 1GB section in L2 page table */
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/***********************************************************/
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static void mmu_map_l2_entry(mmu_section_t *block)
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{
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uint64_t *l2_pt = NULL;
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uint64_t address_start;
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uint64_t address_end;
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uint64_t p_addr;
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/* First initialize the first level descriptor for each 1 GB
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* Bits[47:12] provide the physical base address of the level 2 page table
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*
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* ________________________________________________________________________________
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* | | | | | | | | | |
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* |63|62-61|60| 59|58---52|51----40|39------------------------12|11----2|1------- 0|
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* |NS| AP |XN|PXN|Ignored|UNK|SBZP|Next-level table addr[39:12]|Ignored|Descriptor|
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* |__|_____|__|___|_______|________|____________________________|_______|__________|
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* NS: Used only in secure state
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* AP: Access protection
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*/
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/* Convert the virtual address[38:30] into an index of the L1 page table */
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address_start = (block->vaddress & LPAE_MASK) >> 30;
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/* Check if this 1GB entry has L2 page table mapped already
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* if L1 entry hasn't mapped any L2 page table, allocate a L2 page table for it
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*/
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if((mmu_l1_pagetable[address_start] & PT_TABLE_DESC_BIT) == 0)
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{
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ASSERT(avail_l2_pt);
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/* Get the first l2 empty page table and fill in the L1 PTE with a table descriptor,
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* The l2_pt address bits 12:39 are used for L1 PTE entry
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*/
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l2_pt = empty_l2_pt;
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/* Bits 39.12 of the page table address are mapped into the L1 PTE entry */
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mmu_l1_pagetable[address_start] = ((uint64_t)(uintptr_t)l2_pt & 0x0FFFFFFF000) | MMU_PT_TABLE_DESCRIPTOR;
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/* Advance pointer to next empty l2 page table */
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empty_l2_pt += MMU_L2_PT_SIZE;
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avail_l2_pt--;
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arch_clean_invalidate_cache_range((addr_t) mmu_l1_pagetable, L1_PT_SZ);
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}
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else
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{
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/* Entry has L2 page table mapped already, so just get the existing L2 page table address */
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l2_pt = (uint64_t *) (uintptr_t)(mmu_l1_pagetable[address_start] & 0xFFFFFFF000);
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}
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/* Get the physical address of 2MB sections, bits 21:39 are used to populate the L2 entry */
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p_addr = block->paddress & L2_PT_MASK;
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/* Start index into the L2 page table for this section using the virtual address[29:21]*/
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address_start = (block->vaddress & L2_INDEX_MASK) >> 21;
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/* The end index for the given section. size given is in MB convert it to number of 2MB segments */
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address_end = address_start + ((block->size) >> 1);
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/*
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* ___________________________________________________________________________________________________________________
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* | | | | | | | | | | | | | | | |
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* |63---59|58----55|54|53 |52 |51----40|39--------------21|20----12|11|10|9 8|7 6|5 |4-----------2| 1 0 |
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* |Ignored|Reserved|XN|PXN|Cont|UNK|SBZP|Output addr[39:21]|UNK|SBZP|nG|AF|SH[1:0]|AP[2:1]|NS|AttrIndx[2:0]|Descriptor|
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* |_______|________|__|___|____|________|__________________|________|__|__|_______|_______|__|_____________|__________|
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*/
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/* Map all the 2MB segments in the 1GB section */
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while (address_start < address_end)
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{
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l2_pt[address_start] = (p_addr) | MMU_PT_BLOCK_DESCRIPTOR | MMU_AP_FLAG | block->flags;
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address_start++;
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/* Increment to the next 2MB segment in current L2 page table*/
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p_addr += SIZE_2MB;
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arm_invalidate_tlb();
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}
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arch_clean_invalidate_cache_range((addr_t) mmu_l2_pagetable, (L2_PT_SZ*MMU_L2_PT_SIZE));
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}
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/************************************************************/
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/* MAP 1GB granules in L1 page table */
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/***********************************************************/
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static void mmu_map_l1_entry(mmu_section_t *block)
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{
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uint64_t address_start;
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uint64_t address_end;
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uint64_t p_addr;
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/* Convert our base address into an index into the page table */
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address_start = (block->vaddress & LPAE_MASK) >> 30;
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/* Get the end address into the page table, size is in MB, convert to GB for L1 mapping */
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address_end = address_start + ((block->size) >> 10);
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/* bits 38:30 provide the physical base address of the section */
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p_addr = block->paddress & L1_PT_INDEX;
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while(address_start < address_end)
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{
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/*
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* A Block descriptor for first stage, level one is as follows (Descriptor = 0b01):
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* ___________________________________________________________________________________________________________________
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* | | | | | | | | | | | | | | | |
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* |63---59|58----55|54|53 |52 |51----40|39--------------30|n-1 --12|11|10|9 8|7 6|5 |4-----------2| 1 0 |
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* |Ignored|Reserved|XN|PXN|Cont|UNK/SBZP|Output addr[47:30]|UNK/SBZP|nG|AF|SH[1:0]|AP[2:1]|NS|AttrIndx[2:0]|Descriptor|
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* |_______|________|__|___|____|________|__________________|________|__|__|_______|_______|__|_____________|__________|
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*/
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mmu_l1_pagetable[address_start] = (p_addr) | block->flags | MMU_AP_FLAG | MMU_PT_BLOCK_DESCRIPTOR;
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p_addr += SIZE_1GB; /* Point to next level */
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address_start++;
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arm_invalidate_tlb();
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}
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arch_clean_invalidate_cache_range((addr_t) mmu_l1_pagetable, L1_PT_SZ);
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}
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void arm_mmu_map_entry(mmu_section_t *entry)
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{
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ASSERT(entry);
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if (entry->type == MMU_L1_NS_SECTION_MAPPING)
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mmu_map_l1_entry(entry);
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else if(entry->type == MMU_L2_NS_SECTION_MAPPING)
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mmu_map_l2_entry(entry);
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else
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dprintf(CRITICAL, "Invalid mapping type in the mmu table: %d\n", entry->type);
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}
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void arm_mmu_init(void)
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{
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/* set some mmu specific control bits:
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* access flag disabled, TEX remap disabled, mmu disabled
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*/
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arm_write_cr1(arm_read_cr1() & ~((1<<29)|(1<<28)|(1<<0)));
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platform_init_mmu_mappings();
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/* set up the translation table base */
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arm_write_ttbr((uint32_t)mmu_l1_pagetable);
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/* set up the Memory Attribute Indirection Registers 0 and 1 */
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arm_write_mair0(MAIR0);
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arm_write_mair1(MAIR1);
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/* TTBCR.EAE = 1 & IRGN0 [9:8], ORNG0 bits [11:10]: 01 */
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arm_write_ttbcr(0x80000500);
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/* Enable TRE */
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arm_write_cr1(arm_read_cr1() | (1<<28));
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/* turn on the mmu */
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arm_write_cr1(arm_read_cr1() | 0x1);
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}
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void arch_disable_mmu(void)
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{
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/* Ensure all memory access are complete
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* before disabling MMU
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*/
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dsb();
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arm_write_cr1(arm_read_cr1() & ~(1<<0));
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arm_invalidate_tlb();
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}
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uint64_t virtual_to_physical_mapping(uint32_t vaddr)
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{
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uint32_t l1_index;
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uint64_t *l2_pt = NULL;
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uint32_t l2_index;
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uint32_t offset = 0;
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uint64_t paddr = 0;
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/* Find the L1 index from virtual address */
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l1_index = (vaddr & LPAE_MASK) >> 30;
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if ((mmu_l1_pagetable[l1_index] & MMU_PT_TABLE_DESCRIPTOR) == MMU_PT_TABLE_DESCRIPTOR)
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{
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/* Get the l2 page table address */
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l2_pt = (uint64_t *) (uintptr_t) (mmu_l1_pagetable[l1_index] & 0x0FFFFFFF000);
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/* Get the l2 index from virtual address */
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l2_index = (vaddr & L2_INDEX_MASK) >> 21;
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/* Calculate the offset from vaddr. */
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offset = vaddr & 0x1FFFFF;
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/* Get the physical address bits from 21 to 39 */
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paddr = (l2_pt[l2_index] & L2_PT_MASK) + offset;
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} else if ((mmu_l1_pagetable[l1_index] & MMU_PT_TABLE_DESCRIPTOR) == MMU_PT_BLOCK_DESCRIPTOR)
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{
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/* Calculate the offset from bits 0 to 30 */
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offset = vaddr & 0x3FFFFFFF;
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/* Return the entry from l1 page table */
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paddr = (mmu_l1_pagetable[l1_index] & L1_PT_INDEX) + offset;
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} else
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{
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ASSERT(0);
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}
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return paddr;
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}
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uint32_t physical_to_virtual_mapping(uint64_t paddr)
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{
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uint32_t i, j;
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uint32_t vaddr_index = 0;
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uint32_t vaddr = 0;
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uint64_t paddr_base_l1;
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uint64_t paddr_base_l2;
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uint64_t *l2_pt = NULL;
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bool l1_index_found = false;
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uint32_t l1_index = 0;
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uint32_t offset = 0;
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/* Traverse through the L1 page table to look for block descriptor */
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for (i = 0; i < L1_PT_SZ; i++)
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{
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/* Find the L1 page table index */
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paddr_base_l1 = paddr & L1_PT_INDEX;
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/* If the L1 index is unused continue */
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if ((mmu_l1_pagetable[i] & MMU_PT_TABLE_DESCRIPTOR) == 0)
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continue;
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/* If Its a block entry, find the matching entry and return the index */
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if ((mmu_l1_pagetable[i] & MMU_PT_TABLE_DESCRIPTOR) == MMU_PT_BLOCK_DESCRIPTOR)
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{
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if ((mmu_l1_pagetable[i] & L1_PT_INDEX) == paddr_base_l1)
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{
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offset = paddr - paddr_base_l1;
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vaddr_index = i;
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l1_index_found = true;
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goto end;
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} /* If the entry is table, extract table address */
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} else if ((mmu_l1_pagetable[i] & MMU_PT_TABLE_DESCRIPTOR) == MMU_PT_TABLE_DESCRIPTOR)
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{
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l1_index = i;
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l2_pt = (uint64_t *) (uintptr_t) (mmu_l1_pagetable[l1_index] & 0x0FFFFFFF000);
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paddr_base_l2 = paddr & L2_PT_MASK;
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/* Search the table to find index in L2 page table */
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for (j = 0; j < MMU_L2_PT_SIZE; j++)
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{
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if (paddr_base_l2 == (l2_pt[j] & L2_PT_MASK))
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{
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vaddr_index = j;
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offset = paddr - paddr_base_l2;
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goto end;
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}
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}
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}
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}
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/* If we reach here, that means the addrss is either no mapped or invalid request */
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dprintf(CRITICAL, "The address %llx is not mapped\n", paddr);
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ASSERT(0);
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end:
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/* Convert the index into the virtual address */
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if (l1_index_found)
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vaddr = (vaddr_index << 30);
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else
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vaddr = ((vaddr_index << 21) & L2_INDEX_MASK) + (l1_index << 30);
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vaddr += offset;
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return vaddr;
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}
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#endif // ARM_WITH_MMU
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