573 lines
15 KiB
C
573 lines
15 KiB
C
//------------------------------------------------------------------------------
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// ISC License (ISC)
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//
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// Copyright (c) 2004-2010, The Linux Foundation
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// All rights reserved.
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// Software was previously licensed under ISC license by Qualcomm Atheros, Inc.
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//
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//
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//
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// Permission to use, copy, modify, and/or distribute this software for any
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// purpose with or without fee is hereby granted, provided that the above
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// copyright notice and this permission notice appear in all copies.
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//
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// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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//
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//
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//
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// Author(s): ="Atheros"
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//------------------------------------------------------------------------------
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#include "ar6000_drv.h"
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#include "htc.h"
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#include <linux/fs.h>
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#include "target_reg_table.h"
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#include "host_reg_table.h
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//
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// defines
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//
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#define MAX_FILENAME 1023
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#define EEPROM_WAIT_LIMIT 16
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#define EEPROM_SZ 768
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/* soft mac */
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#define ATH_MAC_LEN 6
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#define ATH_SOFT_MAC_TMP_BUF_LEN 64
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unsigned char mac_addr[ATH_MAC_LEN];
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unsigned char soft_mac_tmp_buf[ATH_SOFT_MAC_TMP_BUF_LEN];
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char *p_mac = NULL;
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/* soft mac */
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//
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// static variables
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//
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static A_UCHAR eeprom_data[EEPROM_SZ];
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static A_UINT32 sys_sleep_reg;
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static HIF_DEVICE *p_bmi_device;
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//
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// Functions
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//
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/* soft mac */
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static int
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wmic_ether_aton(const char *orig, A_UINT8 *eth)
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{
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const char *bufp;
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int i;
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i = 0;
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for(bufp = orig; *bufp != '\0'; ++bufp) {
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unsigned int val;
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unsigned char c = *bufp++;
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if (c >= '0' && c <= '9') val = c - '0';
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else if (c >= 'a' && c <= 'f') val = c - 'a' + 10;
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else if (c >= 'A' && c <= 'F') val = c - 'A' + 10;
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else {
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printk("%s: MAC value is invalid\n", __FUNCTION__);
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break;
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}
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val <<= 4;
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c = *bufp++;
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if (c >= '0' && c <= '9') val |= c - '0';
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else if (c >= 'a' && c <= 'f') val |= c - 'a' + 10;
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else if (c >= 'A' && c <= 'F') val |= c - 'A' + 10;
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else {
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printk("%s: MAC value is invalid\n", __FUNCTION__);
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break;
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}
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eth[i] = (unsigned char) (val & 0377);
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if(++i == ATH_MAC_LEN) {
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/* That's it. Any trailing junk? */
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if (*bufp != '\0') {
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return 0;
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}
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return 1;
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}
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if (*bufp != ':')
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break;
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}
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return 0;
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}
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static void
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update_mac(unsigned char* eeprom, int size, unsigned char* macaddr)
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{
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int i;
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A_UINT16* ptr = (A_UINT16*)(eeprom+4);
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A_UINT16 checksum = 0;
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memcpy(eeprom+10,macaddr,6);
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*ptr = 0;
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ptr = (A_UINT16*)eeprom;
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for (i=0; i<size; i+=2) {
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checksum ^= *ptr++;
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}
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checksum = ~checksum;
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ptr = (A_UINT16*)(eeprom+4);
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*ptr = checksum;
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return;
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}
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/* soft mac */
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/* Read a Target register and return its value. */
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inline void
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BMI_read_reg(A_UINT32 address, A_UINT32 *pvalue)
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{
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BMIReadSOCRegister(p_bmi_device, address, pvalue);
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}
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/* Write a value to a Target register. */
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inline void
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BMI_write_reg(A_UINT32 address, A_UINT32 value)
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{
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BMIWriteSOCRegister(p_bmi_device, address, value);
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}
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/* Read Target memory word and return its value. */
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inline void
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BMI_read_mem(A_UINT32 address, A_UINT32 *pvalue)
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{
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BMIReadMemory(p_bmi_device, address, (A_UCHAR*)(pvalue), 4);
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}
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/* Write a word to a Target memory. */
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inline void
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BMI_write_mem(A_UINT32 address, A_UINT8 *p_data, A_UINT32 sz)
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{
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BMIWriteMemory(p_bmi_device, address, (A_UCHAR*)(p_data), sz);
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}
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/*
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* Enable and configure the Target's Serial Interface
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* so we can access the EEPROM.
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*/
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static void
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enable_SI(HIF_DEVICE *p_device)
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{
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A_UINT32 regval;
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printk("%s\n", __FUNCTION__);
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p_bmi_device = p_device;
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BMI_read_reg(RTC_WMAC_BASE_ADDRESS+WLAN_SYSTEM_SLEEP_OFFSET, &sys_sleep_reg);
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BMI_write_reg(RTC_WMAC_BASE_ADDRESS+WLAN_SYSTEM_SLEEP_OFFSET, SYSTEM_SLEEP_DISABLE_SET(1)); //disable system sleep temporarily
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BMI_read_reg(RTC_SOC_BASE_ADDRESS+CLOCK_CONTROL_OFFSET, ®val);
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regval &= ~CLOCK_CONTROL_SI0_CLK_MASK;
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BMI_write_reg(RTC_SOC_BASE_ADDRESS+CLOCK_CONTROL_OFFSET, regval);
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BMI_read_reg(RTC_SOC_BASE_ADDRESS+RESET_CONTROL_OFFSET, ®val);
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regval &= ~RESET_CONTROL_SI0_RST_MASK;
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BMI_write_reg(RTC_SOC_BASE_ADDRESS+RESET_CONTROL_OFFSET, regval);
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BMI_read_reg(GPIO_BASE_ADDRESS+GPIO_PIN0_OFFSET, ®val);
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regval &= ~GPIO_PIN0_CONFIG_MASK;
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BMI_write_reg(GPIO_BASE_ADDRESS+GPIO_PIN0_OFFSET, regval);
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BMI_read_reg(GPIO_BASE_ADDRESS+GPIO_PIN1_OFFSET, ®val);
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regval &= ~GPIO_PIN1_CONFIG_MASK;
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BMI_write_reg(GPIO_BASE_ADDRESS+GPIO_PIN1_OFFSET, regval);
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/* SI_CONFIG = 0x500a6; */
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regval = SI_CONFIG_BIDIR_OD_DATA_SET(1) |
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SI_CONFIG_I2C_SET(1) |
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SI_CONFIG_POS_SAMPLE_SET(1) |
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SI_CONFIG_INACTIVE_CLK_SET(1) |
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SI_CONFIG_INACTIVE_DATA_SET(1) |
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SI_CONFIG_DIVIDER_SET(6);
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BMI_write_reg(SI_BASE_ADDRESS+SI_CONFIG_OFFSET, regval);
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}
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static void
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disable_SI(void)
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{
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A_UINT32 regval;
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printk("%s\n", __FUNCTION__);
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BMI_write_reg(RTC_SOC_BASE_ADDRESS+RESET_CONTROL_OFFSET, RESET_CONTROL_SI0_RST_MASK);
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BMI_read_reg(RTC_SOC_BASE_ADDRESS+CLOCK_CONTROL_OFFSET, ®val);
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regval |= CLOCK_CONTROL_SI0_CLK_MASK;
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BMI_write_reg(RTC_SOC_BASE_ADDRESS+CLOCK_CONTROL_OFFSET, regval);//Gate SI0 clock
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BMI_write_reg(RTC_WMAC_BASE_ADDRESS+WLAN_SYSTEM_SLEEP_OFFSET, sys_sleep_reg); //restore system sleep setting
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}
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/*
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* Tell the Target to start an 8-byte read from EEPROM,
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* putting the results in Target RX_DATA registers.
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*/
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static void
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request_8byte_read(int offset)
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{
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A_UINT32 regval;
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// printk("%s: request_8byte_read from offset 0x%x\n", __FUNCTION__, offset);
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/* SI_TX_DATA0 = read from offset */
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regval =(0xa1<<16)|
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((offset & 0xff)<<8) |
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(0xa0 | ((offset & 0xff00)>>7));
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BMI_write_reg(SI_BASE_ADDRESS+SI_TX_DATA0_OFFSET, regval);
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regval = SI_CS_START_SET(1) |
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SI_CS_RX_CNT_SET(8) |
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SI_CS_TX_CNT_SET(3);
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BMI_write_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, regval);
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}
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/*
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* Tell the Target to start a 4-byte write to EEPROM,
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* writing values from Target TX_DATA registers.
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*/
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static void
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request_4byte_write(int offset, A_UINT32 data)
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{
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A_UINT32 regval;
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printk("%s: request_4byte_write (0x%x) to offset 0x%x\n", __FUNCTION__, data, offset);
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/* SI_TX_DATA0 = write data to offset */
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regval = ((data & 0xffff) <<16) |
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((offset & 0xff)<<8) |
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(0xa0 | ((offset & 0xff00)>>7));
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BMI_write_reg(SI_BASE_ADDRESS+SI_TX_DATA0_OFFSET, regval);
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regval = data >> 16;
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BMI_write_reg(SI_BASE_ADDRESS+SI_TX_DATA1_OFFSET, regval);
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regval = SI_CS_START_SET(1) |
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SI_CS_RX_CNT_SET(0) |
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SI_CS_TX_CNT_SET(6);
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BMI_write_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, regval);
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}
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/*
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* Check whether or not an EEPROM request that was started
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* earlier has completed yet.
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*/
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static A_BOOL
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request_in_progress(void)
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{
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A_UINT32 regval;
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/* Wait for DONE_INT in SI_CS */
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BMI_read_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, ®val);
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// printk("%s: request in progress SI_CS=0x%x\n", __FUNCTION__, regval);
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if (regval & SI_CS_DONE_ERR_MASK) {
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printk("%s: EEPROM signaled ERROR (0x%x)\n", __FUNCTION__, regval);
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}
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return (!(regval & SI_CS_DONE_INT_MASK));
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}
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/*
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* try to detect the type of EEPROM,16bit address or 8bit address
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*/
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static void eeprom_type_detect(void)
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{
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A_UINT32 regval;
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A_UINT8 i = 0;
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request_8byte_read(0x100);
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/* Wait for DONE_INT in SI_CS */
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do{
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BMI_read_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, ®val);
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if (regval & SI_CS_DONE_ERR_MASK) {
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printk("%s: ERROR : address type was wrongly set\n", __FUNCTION__);
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break;
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}
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if (i++ == EEPROM_WAIT_LIMIT) {
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printk("%s: EEPROM not responding\n", __FUNCTION__);
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}
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} while(!(regval & SI_CS_DONE_INT_MASK));
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}
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/*
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* Extract the results of a completed EEPROM Read request
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* and return them to the caller.
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*/
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inline void
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read_8byte_results(A_UINT32 *data)
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{
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/* Read SI_RX_DATA0 and SI_RX_DATA1 */
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BMI_read_reg(SI_BASE_ADDRESS+SI_RX_DATA0_OFFSET, &data[0]);
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BMI_read_reg(SI_BASE_ADDRESS+SI_RX_DATA1_OFFSET, &data[1]);
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}
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/*
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* Wait for a previously started command to complete.
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* Timeout if the command is takes "too long".
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*/
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static void
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wait_for_eeprom_completion(void)
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{
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int i=0;
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while (request_in_progress()) {
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if (i++ == EEPROM_WAIT_LIMIT) {
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printk("%s: EEPROM not responding\n", __FUNCTION__);
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}
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}
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}
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/*
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* High-level function which starts an 8-byte read,
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* waits for it to complete, and returns the result.
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*/
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static void
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fetch_8bytes(int offset, A_UINT32 *data)
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{
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request_8byte_read(offset);
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wait_for_eeprom_completion();
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read_8byte_results(data);
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/* Clear any pending intr */
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BMI_write_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, SI_CS_DONE_INT_MASK);
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}
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/*
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* High-level function which starts a 4-byte write,
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* and waits for it to complete.
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*/
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inline void
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commit_4bytes(int offset, A_UINT32 data)
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{
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request_4byte_write(offset, data);
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wait_for_eeprom_completion();
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}
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/* ATHENV */
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#ifdef ANDROID_ENV
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void eeprom_ar6000_transfer(HIF_DEVICE *device, char *fake_file, char *p_mac)
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{
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A_UINT32 first_word;
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A_UINT32 board_data_addr;
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int i;
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printk("%s: Enter\n", __FUNCTION__);
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enable_SI(device);
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eeprom_type_detect();
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if (fake_file) {
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/*
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* Transfer from file to Target RAM.
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* Fetch source data from file.
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*/
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mm_segment_t oldfs;
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struct file *filp;
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struct inode *inode = NULL;
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int length;
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/* open file */
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oldfs = get_fs();
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set_fs(KERNEL_DS);
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filp = filp_open(fake_file, O_RDONLY, S_IRUSR);
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if (IS_ERR(filp)) {
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printk("%s: file %s filp_open error\n", __FUNCTION__, fake_file);
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set_fs(oldfs);
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return;
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}
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if (!filp->f_op) {
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printk("%s: File Operation Method Error\n", __FUNCTION__);
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filp_close(filp, NULL);
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set_fs(oldfs);
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return;
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}
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inode = GET_INODE_FROM_FILEP(filep);
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if (!inode) {
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printk("%s: Get inode from filp failed\n", __FUNCTION__);
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filp_close(filp, NULL);
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set_fs(oldfs);
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return;
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}
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printk("%s file offset opsition: %xh\n", __FUNCTION__, (unsigned)filp->f_pos);
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/* file's size */
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length = i_size_read(inode->i_mapping->host);
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printk("%s: length=%d\n", __FUNCTION__, length);
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if (length != EEPROM_SZ) {
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printk("%s: The file's size is not as expected\n", __FUNCTION__);
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filp_close(filp, NULL);
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set_fs(oldfs);
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return;
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}
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/* read data */
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if (filp->f_op->read(filp, eeprom_data, length, &filp->f_pos) != length) {
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printk("%s: file read error\n", __FUNCTION__);
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filp_close(filp, NULL);
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set_fs(oldfs);
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return;
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}
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/* read data out successfully */
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filp_close(filp, NULL);
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set_fs(oldfs);
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} else {
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/*
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* Read from EEPROM to file OR transfer from EEPROM to Target RAM.
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* Fetch EEPROM_SZ Bytes of Board Data, 8 bytes at a time.
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*/
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fetch_8bytes(0, (A_UINT32 *)(&eeprom_data[0]));
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/* Check the first word of EEPROM for validity */
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first_word = *((A_UINT32 *)eeprom_data);
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if ((first_word == 0) || (first_word == 0xffffffff)) {
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printk("Did not find EEPROM with valid Board Data.\n");
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}
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for (i=8; i<EEPROM_SZ; i+=8) {
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fetch_8bytes(i, (A_UINT32 *)(&eeprom_data[i]));
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}
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}
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/* soft mac */
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if (p_mac) {
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mm_segment_t oldfs;
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struct file *filp;
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struct inode *inode = NULL;
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int length;
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/* open file */
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oldfs = get_fs();
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set_fs(KERNEL_DS);
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filp = filp_open(p_mac, O_RDONLY, S_IRUSR);
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printk("%s try to open file %s\n", __FUNCTION__, p_mac);
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if (IS_ERR(filp)) {
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printk("%s: file %s filp_open error\n", __FUNCTION__, p_mac);
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set_fs(oldfs);
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return;
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}
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if (!filp->f_op) {
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printk("%s: File Operation Method Error\n", __FUNCTION__);
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filp_close(filp, NULL);
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set_fs(oldfs);
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return;
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}
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inode = GET_INODE_FROM_FILEP(filep);
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if (!inode) {
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printk("%s: Get inode from filp failed\n", __FUNCTION__);
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filp_close(filp, NULL);
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set_fs(oldfs);
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return;
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}
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printk("%s file offset opsition: %xh\n", __FUNCTION__, (unsigned)filp->f_pos);
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/* file's size */
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length = i_size_read(inode->i_mapping->host);
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printk("%s: length=%d\n", __FUNCTION__, length);
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if (length > ATH_SOFT_MAC_TMP_BUF_LEN) {
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printk("%s: MAC file's size is not as expected\n", __FUNCTION__);
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filp_close(filp, NULL);
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set_fs(oldfs);
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return;
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}
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/* read data */
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if (filp->f_op->read(filp, soft_mac_tmp_buf, length, &filp->f_pos) != length) {
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printk("%s: file read error\n", __FUNCTION__);
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filp_close(filp, NULL);
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set_fs(oldfs);
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return;
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}
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#if 0
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/* the data we just read */
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printk("%s: mac address from the file:\n", __FUNCTION__);
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for (i = 0; i < length; i++)
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printk("[%c(0x%x)],", soft_mac_tmp_buf[i], soft_mac_tmp_buf[i]);
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printk("\n");
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#endif
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/* read data out successfully */
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filp_close(filp, NULL);
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set_fs(oldfs);
|
|
|
|
/* convert mac address */
|
|
if (!wmic_ether_aton(soft_mac_tmp_buf, mac_addr)) {
|
|
printk("%s: convert mac value fail\n", __FUNCTION__);
|
|
return;
|
|
}
|
|
|
|
#if 0
|
|
/* the converted mac address */
|
|
printk("%s: the converted mac value\n", __FUNCTION__);
|
|
for (i = 0; i < ATH_MAC_LEN; i++)
|
|
printk("[0x%x],", mac_addr[i]);
|
|
printk("\n");
|
|
#endif
|
|
}
|
|
/* soft mac */
|
|
|
|
/* Determine where in Target RAM to write Board Data */
|
|
BMI_read_mem( AR6002_HOST_INTEREST_ITEM_ADDRESS(hi_board_data), &board_data_addr);
|
|
if (board_data_addr == 0) {
|
|
printk("hi_board_data is zero\n");
|
|
}
|
|
|
|
/* soft mac */
|
|
#if 1
|
|
/* Update MAC address in RAM */
|
|
if (p_mac) {
|
|
update_mac(eeprom_data, EEPROM_SZ, mac_addr);
|
|
}
|
|
#endif
|
|
#if 0
|
|
/* mac address in eeprom array */
|
|
printk("%s: mac values in eeprom array\n", __FUNCTION__);
|
|
for (i = 10; i < 10 + 6; i++)
|
|
printk("[0x%x],", eeprom_data[i]);
|
|
printk("\n");
|
|
#endif
|
|
/* soft mac */
|
|
|
|
/* Write EEPROM data to Target RAM */
|
|
BMI_write_mem(board_data_addr, ((A_UINT8 *)eeprom_data), EEPROM_SZ);
|
|
|
|
/* Record the fact that Board Data IS initialized */
|
|
{
|
|
A_UINT32 one = 1;
|
|
BMI_write_mem(AR6002_HOST_INTEREST_ITEM_ADDRESS(hi_board_data_initialized),
|
|
(A_UINT8 *)&one, sizeof(A_UINT32));
|
|
}
|
|
|
|
disable_SI();
|
|
}
|