446 lines
14 KiB
C
446 lines
14 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
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*
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* Portions of this file are derived from the ipw3945 project, as well
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* as portions of the ieee80211 subsystem header files.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* Intel Linux Wireless <ilw@linux.intel.com>
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* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*****************************************************************************/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <net/mac80211.h>
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#include "iwl-eeprom.h"
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#include "iwl-dev.h"
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#include "iwl-agn.h"
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#include "iwl-core.h"
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#include "iwl-io.h"
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#include "iwl-commands.h"
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#include "iwl-debug.h"
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#include "iwl-power.h"
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#include "iwl-trans.h"
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#include "iwl-shared.h"
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/*
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* Setting power level allows the card to go to sleep when not busy.
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*
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* We calculate a sleep command based on the required latency, which
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* we get from mac80211. In order to handle thermal throttling, we can
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* also use pre-defined power levels.
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*/
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/*
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* This defines the old power levels. They are still used by default
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* (level 1) and for thermal throttle (levels 3 through 5)
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*/
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struct iwl_power_vec_entry {
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struct iwl_powertable_cmd cmd;
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u8 no_dtim; /* number of skip dtim */
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};
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#define IWL_DTIM_RANGE_0_MAX 2
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#define IWL_DTIM_RANGE_1_MAX 10
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#define NOSLP cpu_to_le16(0), 0, 0
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#define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK, 0, 0
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#define ASLP (IWL_POWER_POWER_SAVE_ENA_MSK | \
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IWL_POWER_POWER_MANAGEMENT_ENA_MSK | \
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IWL_POWER_ADVANCE_PM_ENA_MSK)
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#define ASLP_TOUT(T) cpu_to_le32(T)
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#define TU_TO_USEC 1024
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#define SLP_TOUT(T) cpu_to_le32((T) * TU_TO_USEC)
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#define SLP_VEC(X0, X1, X2, X3, X4) {cpu_to_le32(X0), \
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cpu_to_le32(X1), \
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cpu_to_le32(X2), \
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cpu_to_le32(X3), \
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cpu_to_le32(X4)}
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/* default power management (not Tx power) table values */
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/* for DTIM period 0 through IWL_DTIM_RANGE_0_MAX */
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/* DTIM 0 - 2 */
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static const struct iwl_power_vec_entry range_0[IWL_POWER_NUM] = {
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{{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 1, 2, 2, 0xFF)}, 0},
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{{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(1, 2, 2, 2, 0xFF)}, 0},
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{{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 2, 2, 2, 0xFF)}, 0},
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{{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 2, 4, 4, 0xFF)}, 1},
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{{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(2, 2, 4, 6, 0xFF)}, 2}
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};
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/* for DTIM period IWL_DTIM_RANGE_0_MAX + 1 through IWL_DTIM_RANGE_1_MAX */
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/* DTIM 3 - 10 */
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static const struct iwl_power_vec_entry range_1[IWL_POWER_NUM] = {
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{{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
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{{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(1, 2, 3, 4, 7)}, 0},
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{{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 4, 6, 7, 9)}, 0},
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{{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 4, 6, 9, 10)}, 1},
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{{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(2, 4, 6, 10, 10)}, 2}
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};
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/* for DTIM period > IWL_DTIM_RANGE_1_MAX */
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/* DTIM 11 - */
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static const struct iwl_power_vec_entry range_2[IWL_POWER_NUM] = {
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{{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
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{{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
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{{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
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{{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
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{{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
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};
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/* advance power management */
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/* DTIM 0 - 2 */
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static const struct iwl_power_vec_entry apm_range_0[IWL_POWER_NUM] = {
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{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
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SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
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{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
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SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
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{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
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SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
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{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
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SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
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{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
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SLP_VEC(1, 2, 6, 8, 0xFF), ASLP_TOUT(2)}, 2}
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};
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/* for DTIM period IWL_DTIM_RANGE_0_MAX + 1 through IWL_DTIM_RANGE_1_MAX */
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/* DTIM 3 - 10 */
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static const struct iwl_power_vec_entry apm_range_1[IWL_POWER_NUM] = {
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{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
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SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
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{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
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SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
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{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
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SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
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{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
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SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
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{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
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SLP_VEC(1, 2, 6, 8, 0xFF), 0}, 2}
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};
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/* for DTIM period > IWL_DTIM_RANGE_1_MAX */
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/* DTIM 11 - */
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static const struct iwl_power_vec_entry apm_range_2[IWL_POWER_NUM] = {
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{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
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SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
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{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
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SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
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{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
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SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
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{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
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SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
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{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
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SLP_VEC(1, 2, 6, 8, 0xFF), ASLP_TOUT(2)}, 2}
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};
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static void iwl_static_sleep_cmd(struct iwl_priv *priv,
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struct iwl_powertable_cmd *cmd,
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enum iwl_power_level lvl, int period)
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{
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const struct iwl_power_vec_entry *table;
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int max_sleep[IWL_POWER_VEC_SIZE] = { 0 };
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int i;
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u8 skip;
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u32 slp_itrvl;
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if (cfg(priv)->adv_pm) {
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table = apm_range_2;
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if (period <= IWL_DTIM_RANGE_1_MAX)
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table = apm_range_1;
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if (period <= IWL_DTIM_RANGE_0_MAX)
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table = apm_range_0;
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} else {
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table = range_2;
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if (period <= IWL_DTIM_RANGE_1_MAX)
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table = range_1;
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if (period <= IWL_DTIM_RANGE_0_MAX)
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table = range_0;
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}
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if (WARN_ON(lvl < 0 || lvl >= IWL_POWER_NUM))
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memset(cmd, 0, sizeof(*cmd));
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else
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*cmd = table[lvl].cmd;
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if (period == 0) {
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skip = 0;
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period = 1;
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for (i = 0; i < IWL_POWER_VEC_SIZE; i++)
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max_sleep[i] = 1;
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} else {
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skip = table[lvl].no_dtim;
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for (i = 0; i < IWL_POWER_VEC_SIZE; i++)
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max_sleep[i] = le32_to_cpu(cmd->sleep_interval[i]);
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max_sleep[IWL_POWER_VEC_SIZE - 1] = skip + 1;
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}
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slp_itrvl = le32_to_cpu(cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]);
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/* figure out the listen interval based on dtim period and skip */
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if (slp_itrvl == 0xFF)
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cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1] =
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cpu_to_le32(period * (skip + 1));
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slp_itrvl = le32_to_cpu(cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]);
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if (slp_itrvl > period)
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cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1] =
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cpu_to_le32((slp_itrvl / period) * period);
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if (skip)
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cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
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else
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cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
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if (cfg(priv)->base_params->shadow_reg_enable)
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cmd->flags |= IWL_POWER_SHADOW_REG_ENA;
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else
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cmd->flags &= ~IWL_POWER_SHADOW_REG_ENA;
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if (iwl_advanced_bt_coexist(priv)) {
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if (!cfg(priv)->bt_params->bt_sco_disable)
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cmd->flags |= IWL_POWER_BT_SCO_ENA;
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else
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cmd->flags &= ~IWL_POWER_BT_SCO_ENA;
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}
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slp_itrvl = le32_to_cpu(cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]);
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if (slp_itrvl > IWL_CONN_MAX_LISTEN_INTERVAL)
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cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1] =
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cpu_to_le32(IWL_CONN_MAX_LISTEN_INTERVAL);
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/* enforce max sleep interval */
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for (i = IWL_POWER_VEC_SIZE - 1; i >= 0 ; i--) {
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if (le32_to_cpu(cmd->sleep_interval[i]) >
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(max_sleep[i] * period))
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cmd->sleep_interval[i] =
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cpu_to_le32(max_sleep[i] * period);
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if (i != (IWL_POWER_VEC_SIZE - 1)) {
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if (le32_to_cpu(cmd->sleep_interval[i]) >
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le32_to_cpu(cmd->sleep_interval[i+1]))
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cmd->sleep_interval[i] =
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cmd->sleep_interval[i+1];
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}
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}
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if (priv->power_data.bus_pm)
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cmd->flags |= IWL_POWER_PCI_PM_MSK;
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else
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cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
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IWL_DEBUG_POWER(priv, "numSkipDtim = %u, dtimPeriod = %d\n",
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skip, period);
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IWL_DEBUG_POWER(priv, "Sleep command for index %d\n", lvl + 1);
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}
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static void iwl_power_sleep_cam_cmd(struct iwl_priv *priv,
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struct iwl_powertable_cmd *cmd)
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{
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memset(cmd, 0, sizeof(*cmd));
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if (priv->power_data.bus_pm)
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cmd->flags |= IWL_POWER_PCI_PM_MSK;
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IWL_DEBUG_POWER(priv, "Sleep command for CAM\n");
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}
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static void iwl_power_fill_sleep_cmd(struct iwl_priv *priv,
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struct iwl_powertable_cmd *cmd,
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int dynps_ms, int wakeup_period)
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{
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/*
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* These are the original power level 3 sleep successions. The
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* device may behave better with such succession and was also
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* only tested with that. Just like the original sleep commands,
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* also adjust the succession here to the wakeup_period below.
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* The ranges are the same as for the sleep commands, 0-2, 3-9
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* and >10, which is selected based on the DTIM interval for
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* the sleep index but here we use the wakeup period since that
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* is what we need to do for the latency requirements.
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*/
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static const u8 slp_succ_r0[IWL_POWER_VEC_SIZE] = { 2, 2, 2, 2, 2 };
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static const u8 slp_succ_r1[IWL_POWER_VEC_SIZE] = { 2, 4, 6, 7, 9 };
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static const u8 slp_succ_r2[IWL_POWER_VEC_SIZE] = { 2, 7, 9, 9, 0xFF };
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const u8 *slp_succ = slp_succ_r0;
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int i;
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if (wakeup_period > IWL_DTIM_RANGE_0_MAX)
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slp_succ = slp_succ_r1;
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if (wakeup_period > IWL_DTIM_RANGE_1_MAX)
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slp_succ = slp_succ_r2;
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memset(cmd, 0, sizeof(*cmd));
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cmd->flags = IWL_POWER_DRIVER_ALLOW_SLEEP_MSK |
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IWL_POWER_FAST_PD; /* no use seeing frames for others */
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if (priv->power_data.bus_pm)
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cmd->flags |= IWL_POWER_PCI_PM_MSK;
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if (cfg(priv)->base_params->shadow_reg_enable)
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cmd->flags |= IWL_POWER_SHADOW_REG_ENA;
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else
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cmd->flags &= ~IWL_POWER_SHADOW_REG_ENA;
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if (iwl_advanced_bt_coexist(priv)) {
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if (!cfg(priv)->bt_params->bt_sco_disable)
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cmd->flags |= IWL_POWER_BT_SCO_ENA;
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else
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cmd->flags &= ~IWL_POWER_BT_SCO_ENA;
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}
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cmd->rx_data_timeout = cpu_to_le32(1000 * dynps_ms);
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cmd->tx_data_timeout = cpu_to_le32(1000 * dynps_ms);
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for (i = 0; i < IWL_POWER_VEC_SIZE; i++)
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cmd->sleep_interval[i] =
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cpu_to_le32(min_t(int, slp_succ[i], wakeup_period));
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IWL_DEBUG_POWER(priv, "Automatic sleep command\n");
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}
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static int iwl_set_power(struct iwl_priv *priv, struct iwl_powertable_cmd *cmd)
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{
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IWL_DEBUG_POWER(priv, "Sending power/sleep command\n");
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IWL_DEBUG_POWER(priv, "Flags value = 0x%08X\n", cmd->flags);
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IWL_DEBUG_POWER(priv, "Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
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IWL_DEBUG_POWER(priv, "Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
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IWL_DEBUG_POWER(priv, "Sleep interval vector = { %d , %d , %d , %d , %d }\n",
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le32_to_cpu(cmd->sleep_interval[0]),
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le32_to_cpu(cmd->sleep_interval[1]),
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le32_to_cpu(cmd->sleep_interval[2]),
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le32_to_cpu(cmd->sleep_interval[3]),
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le32_to_cpu(cmd->sleep_interval[4]));
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return iwl_dvm_send_cmd_pdu(priv, POWER_TABLE_CMD, CMD_SYNC,
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sizeof(struct iwl_powertable_cmd), cmd);
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}
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static void iwl_power_build_cmd(struct iwl_priv *priv,
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struct iwl_powertable_cmd *cmd)
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{
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bool enabled = priv->hw->conf.flags & IEEE80211_CONF_PS;
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int dtimper;
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dtimper = priv->hw->conf.ps_dtim_period ?: 1;
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if (priv->wowlan)
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iwl_static_sleep_cmd(priv, cmd, IWL_POWER_INDEX_5, dtimper);
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else if (!cfg(priv)->base_params->no_idle_support &&
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priv->hw->conf.flags & IEEE80211_CONF_IDLE)
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iwl_static_sleep_cmd(priv, cmd, IWL_POWER_INDEX_5, 20);
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else if (iwl_tt_is_low_power_state(priv)) {
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/* in thermal throttling low power state */
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iwl_static_sleep_cmd(priv, cmd,
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iwl_tt_current_power_mode(priv), dtimper);
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} else if (!enabled)
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iwl_power_sleep_cam_cmd(priv, cmd);
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else if (priv->power_data.debug_sleep_level_override >= 0)
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iwl_static_sleep_cmd(priv, cmd,
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priv->power_data.debug_sleep_level_override,
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dtimper);
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else if (iwlagn_mod_params.no_sleep_autoadjust) {
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if (iwlagn_mod_params.power_level > IWL_POWER_INDEX_1 &&
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iwlagn_mod_params.power_level <= IWL_POWER_INDEX_5)
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iwl_static_sleep_cmd(priv, cmd,
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iwlagn_mod_params.power_level, dtimper);
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else
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iwl_static_sleep_cmd(priv, cmd,
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IWL_POWER_INDEX_1, dtimper);
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} else
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iwl_power_fill_sleep_cmd(priv, cmd,
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priv->hw->conf.dynamic_ps_timeout,
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priv->hw->conf.max_sleep_period);
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}
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int iwl_power_set_mode(struct iwl_priv *priv, struct iwl_powertable_cmd *cmd,
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bool force)
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{
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int ret;
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bool update_chains;
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lockdep_assert_held(&priv->mutex);
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/* Don't update the RX chain when chain noise calibration is running */
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update_chains = priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE ||
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|
priv->chain_noise_data.state == IWL_CHAIN_NOISE_ALIVE;
|
|
|
|
if (!memcmp(&priv->power_data.sleep_cmd, cmd, sizeof(*cmd)) && !force)
|
|
return 0;
|
|
|
|
if (!iwl_is_ready_rf(priv))
|
|
return -EIO;
|
|
|
|
/* scan complete use sleep_power_next, need to be updated */
|
|
memcpy(&priv->power_data.sleep_cmd_next, cmd, sizeof(*cmd));
|
|
if (test_bit(STATUS_SCANNING, &priv->status) && !force) {
|
|
IWL_DEBUG_INFO(priv, "Defer power set mode while scanning\n");
|
|
return 0;
|
|
}
|
|
|
|
if (cmd->flags & IWL_POWER_DRIVER_ALLOW_SLEEP_MSK)
|
|
set_bit(STATUS_POWER_PMI, &priv->shrd->status);
|
|
|
|
ret = iwl_set_power(priv, cmd);
|
|
if (!ret) {
|
|
if (!(cmd->flags & IWL_POWER_DRIVER_ALLOW_SLEEP_MSK))
|
|
clear_bit(STATUS_POWER_PMI, &priv->shrd->status);
|
|
|
|
if (update_chains)
|
|
iwl_update_chain_flags(priv);
|
|
else
|
|
IWL_DEBUG_POWER(priv,
|
|
"Cannot update the power, chain noise "
|
|
"calibration running: %d\n",
|
|
priv->chain_noise_data.state);
|
|
|
|
memcpy(&priv->power_data.sleep_cmd, cmd, sizeof(*cmd));
|
|
} else
|
|
IWL_ERR(priv, "set power fail, ret = %d", ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
int iwl_power_update_mode(struct iwl_priv *priv, bool force)
|
|
{
|
|
struct iwl_powertable_cmd cmd;
|
|
|
|
iwl_power_build_cmd(priv, &cmd);
|
|
return iwl_power_set_mode(priv, &cmd, force);
|
|
}
|
|
|
|
/* initialize to default */
|
|
void iwl_power_initialize(struct iwl_priv *priv)
|
|
{
|
|
priv->power_data.bus_pm = trans(priv)->pm_support;
|
|
|
|
priv->power_data.debug_sleep_level_override = -1;
|
|
|
|
memset(&priv->power_data.sleep_cmd, 0,
|
|
sizeof(priv->power_data.sleep_cmd));
|
|
}
|