315 lines
10 KiB
C
315 lines
10 KiB
C
/*
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* drivers/net/ethernet/ibm/emac/emac.h
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*
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* Register definitions for PowerPC 4xx on-chip ethernet contoller
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*
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* Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
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* <benh@kernel.crashing.org>
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*
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* Based on the arch/ppc version of the driver:
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*
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* Copyright (c) 2004, 2005 Zultys Technologies.
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* Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
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*
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* Based on original work by
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* Matt Porter <mporter@kernel.crashing.org>
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* Armin Kuster <akuster@mvista.com>
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* Copyright 2002-2004 MontaVista Software Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#ifndef __IBM_NEWEMAC_H
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#define __IBM_NEWEMAC_H
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#include <linux/types.h>
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#include <linux/phy.h>
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/* EMAC registers Write Access rules */
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struct emac_regs {
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/* Common registers across all EMAC implementations. */
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u32 mr0; /* Special */
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u32 mr1; /* Reset */
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u32 tmr0; /* Special */
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u32 tmr1; /* Special */
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u32 rmr; /* Reset */
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u32 isr; /* Always */
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u32 iser; /* Reset */
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u32 iahr; /* Reset, R, T */
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u32 ialr; /* Reset, R, T */
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u32 vtpid; /* Reset, R, T */
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u32 vtci; /* Reset, R, T */
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u32 ptr; /* Reset, T */
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union {
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/* Registers unique to EMAC4 implementations */
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struct {
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u32 iaht1; /* Reset, R */
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u32 iaht2; /* Reset, R */
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u32 iaht3; /* Reset, R */
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u32 iaht4; /* Reset, R */
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u32 gaht1; /* Reset, R */
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u32 gaht2; /* Reset, R */
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u32 gaht3; /* Reset, R */
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u32 gaht4; /* Reset, R */
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} emac4;
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/* Registers unique to EMAC4SYNC implementations */
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struct {
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u32 mahr; /* Reset, R, T */
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u32 malr; /* Reset, R, T */
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u32 mmahr; /* Reset, R, T */
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u32 mmalr; /* Reset, R, T */
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u32 rsvd0[4];
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} emac4sync;
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} u0;
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/* Common registers across all EMAC implementations. */
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u32 lsah;
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u32 lsal;
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u32 ipgvr; /* Reset, T */
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u32 stacr; /* Special */
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u32 trtr; /* Special */
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u32 rwmr; /* Reset */
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u32 octx;
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u32 ocrx;
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union {
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/* Registers unique to EMAC4 implementations */
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struct {
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u32 ipcr;
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} emac4;
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/* Registers unique to EMAC4SYNC implementations */
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struct {
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u32 rsvd1;
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u32 revid;
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u32 rsvd2[2];
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u32 iaht1; /* Reset, R */
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u32 iaht2; /* Reset, R */
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u32 iaht3; /* Reset, R */
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u32 iaht4; /* Reset, R */
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u32 iaht5; /* Reset, R */
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u32 iaht6; /* Reset, R */
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u32 iaht7; /* Reset, R */
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u32 iaht8; /* Reset, R */
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u32 gaht1; /* Reset, R */
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u32 gaht2; /* Reset, R */
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u32 gaht3; /* Reset, R */
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u32 gaht4; /* Reset, R */
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u32 gaht5; /* Reset, R */
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u32 gaht6; /* Reset, R */
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u32 gaht7; /* Reset, R */
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u32 gaht8; /* Reset, R */
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u32 tpc; /* Reset, T */
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} emac4sync;
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} u1;
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};
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/*
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* PHY mode settings (EMAC <-> ZMII/RGMII bridge <-> PHY)
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*/
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#define PHY_MODE_NA PHY_INTERFACE_MODE_NA
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#define PHY_MODE_MII PHY_INTERFACE_MODE_MII
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#define PHY_MODE_RMII PHY_INTERFACE_MODE_RMII
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#define PHY_MODE_SMII PHY_INTERFACE_MODE_SMII
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#define PHY_MODE_RGMII PHY_INTERFACE_MODE_RGMII
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#define PHY_MODE_TBI PHY_INTERFACE_MODE_TBI
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#define PHY_MODE_GMII PHY_INTERFACE_MODE_GMII
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#define PHY_MODE_RTBI PHY_INTERFACE_MODE_RTBI
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#define PHY_MODE_SGMII PHY_INTERFACE_MODE_SGMII
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/* EMACx_MR0 */
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#define EMAC_MR0_RXI 0x80000000
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#define EMAC_MR0_TXI 0x40000000
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#define EMAC_MR0_SRST 0x20000000
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#define EMAC_MR0_TXE 0x10000000
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#define EMAC_MR0_RXE 0x08000000
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#define EMAC_MR0_WKE 0x04000000
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/* EMACx_MR1 */
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#define EMAC_MR1_FDE 0x80000000
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#define EMAC_MR1_ILE 0x40000000
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#define EMAC_MR1_VLE 0x20000000
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#define EMAC_MR1_EIFC 0x10000000
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#define EMAC_MR1_APP 0x08000000
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#define EMAC_MR1_IST 0x01000000
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#define EMAC_MR1_MF_MASK 0x00c00000
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#define EMAC_MR1_MF_10 0x00000000
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#define EMAC_MR1_MF_100 0x00400000
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#define EMAC_MR1_MF_1000 0x00800000
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#define EMAC_MR1_MF_1000GPCS 0x00c00000
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#define EMAC_MR1_MF_IPPA(id) (((id) & 0x1f) << 6)
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#define EMAC_MR1_RFS_4K 0x00300000
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#define EMAC_MR1_RFS_16K 0x00000000
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#define EMAC_MR1_TFS_2K 0x00080000
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#define EMAC_MR1_TR0_MULT 0x00008000
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#define EMAC_MR1_JPSM 0x00000000
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#define EMAC_MR1_MWSW_001 0x00000000
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#define EMAC_MR1_BASE(opb) (EMAC_MR1_TFS_2K | EMAC_MR1_TR0_MULT)
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#define EMAC4_MR1_RFS_2K 0x00100000
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#define EMAC4_MR1_RFS_4K 0x00180000
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#define EMAC4_MR1_RFS_16K 0x00280000
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#define EMAC4_MR1_TFS_2K 0x00020000
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#define EMAC4_MR1_TFS_4K 0x00030000
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#define EMAC4_MR1_TFS_16K 0x00050000
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#define EMAC4_MR1_TR 0x00008000
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#define EMAC4_MR1_MWSW_001 0x00001000
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#define EMAC4_MR1_JPSM 0x00000800
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#define EMAC4_MR1_OBCI_MASK 0x00000038
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#define EMAC4_MR1_OBCI_50 0x00000000
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#define EMAC4_MR1_OBCI_66 0x00000008
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#define EMAC4_MR1_OBCI_83 0x00000010
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#define EMAC4_MR1_OBCI_100 0x00000018
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#define EMAC4_MR1_OBCI_100P 0x00000020
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#define EMAC4_MR1_OBCI(freq) ((freq) <= 50 ? EMAC4_MR1_OBCI_50 : \
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(freq) <= 66 ? EMAC4_MR1_OBCI_66 : \
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(freq) <= 83 ? EMAC4_MR1_OBCI_83 : \
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(freq) <= 100 ? EMAC4_MR1_OBCI_100 : \
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EMAC4_MR1_OBCI_100P)
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/* EMACx_TMR0 */
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#define EMAC_TMR0_GNP 0x80000000
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#define EMAC_TMR0_DEFAULT 0x00000000
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#define EMAC4_TMR0_TFAE_2_32 0x00000001
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#define EMAC4_TMR0_TFAE_4_64 0x00000002
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#define EMAC4_TMR0_TFAE_8_128 0x00000003
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#define EMAC4_TMR0_TFAE_16_256 0x00000004
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#define EMAC4_TMR0_TFAE_32_512 0x00000005
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#define EMAC4_TMR0_TFAE_64_1024 0x00000006
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#define EMAC4_TMR0_TFAE_128_2048 0x00000007
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#define EMAC4_TMR0_DEFAULT EMAC4_TMR0_TFAE_2_32
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#define EMAC_TMR0_XMIT (EMAC_TMR0_GNP | EMAC_TMR0_DEFAULT)
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#define EMAC4_TMR0_XMIT (EMAC_TMR0_GNP | EMAC4_TMR0_DEFAULT)
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/* EMACx_TMR1 */
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#define EMAC_TMR1(l,h) (((l) << 27) | (((h) & 0xff) << 16))
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#define EMAC4_TMR1(l,h) (((l) << 27) | (((h) & 0x3ff) << 14))
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/* EMACx_RMR */
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#define EMAC_RMR_SP 0x80000000
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#define EMAC_RMR_SFCS 0x40000000
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#define EMAC_RMR_RRP 0x20000000
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#define EMAC_RMR_RFP 0x10000000
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#define EMAC_RMR_ROP 0x08000000
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#define EMAC_RMR_RPIR 0x04000000
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#define EMAC_RMR_PPP 0x02000000
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#define EMAC_RMR_PME 0x01000000
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#define EMAC_RMR_PMME 0x00800000
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#define EMAC_RMR_IAE 0x00400000
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#define EMAC_RMR_MIAE 0x00200000
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#define EMAC_RMR_BAE 0x00100000
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#define EMAC_RMR_MAE 0x00080000
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#define EMAC_RMR_BASE 0x00000000
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#define EMAC4_RMR_RFAF_2_32 0x00000001
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#define EMAC4_RMR_RFAF_4_64 0x00000002
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#define EMAC4_RMR_RFAF_8_128 0x00000003
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#define EMAC4_RMR_RFAF_16_256 0x00000004
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#define EMAC4_RMR_RFAF_32_512 0x00000005
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#define EMAC4_RMR_RFAF_64_1024 0x00000006
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#define EMAC4_RMR_RFAF_128_2048 0x00000007
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#define EMAC4_RMR_BASE EMAC4_RMR_RFAF_128_2048
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#define EMAC4_RMR_MJS_MASK 0x0001fff8
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#define EMAC4_RMR_MJS(s) (((s) << 3) & EMAC4_RMR_MJS_MASK)
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/* EMACx_ISR & EMACx_ISER */
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#define EMAC4_ISR_TXPE 0x20000000
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#define EMAC4_ISR_RXPE 0x10000000
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#define EMAC4_ISR_TXUE 0x08000000
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#define EMAC4_ISR_RXOE 0x04000000
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#define EMAC_ISR_OVR 0x02000000
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#define EMAC_ISR_PP 0x01000000
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#define EMAC_ISR_BP 0x00800000
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#define EMAC_ISR_RP 0x00400000
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#define EMAC_ISR_SE 0x00200000
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#define EMAC_ISR_ALE 0x00100000
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#define EMAC_ISR_BFCS 0x00080000
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#define EMAC_ISR_PTLE 0x00040000
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#define EMAC_ISR_ORE 0x00020000
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#define EMAC_ISR_IRE 0x00010000
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#define EMAC_ISR_SQE 0x00000080
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#define EMAC_ISR_TE 0x00000040
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#define EMAC_ISR_MOS 0x00000002
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#define EMAC_ISR_MOF 0x00000001
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/* EMACx_STACR */
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#define EMAC_STACR_PHYD_MASK 0xffff
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#define EMAC_STACR_PHYD_SHIFT 16
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#define EMAC_STACR_OC 0x00008000
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#define EMAC_STACR_PHYE 0x00004000
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#define EMAC_STACR_STAC_MASK 0x00003000
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#define EMAC_STACR_STAC_READ 0x00001000
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#define EMAC_STACR_STAC_WRITE 0x00002000
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#define EMAC_STACR_OPBC_MASK 0x00000C00
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#define EMAC_STACR_OPBC_50 0x00000000
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#define EMAC_STACR_OPBC_66 0x00000400
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#define EMAC_STACR_OPBC_83 0x00000800
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#define EMAC_STACR_OPBC_100 0x00000C00
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#define EMAC_STACR_OPBC(freq) ((freq) <= 50 ? EMAC_STACR_OPBC_50 : \
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(freq) <= 66 ? EMAC_STACR_OPBC_66 : \
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(freq) <= 83 ? EMAC_STACR_OPBC_83 : EMAC_STACR_OPBC_100)
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#define EMAC_STACR_BASE(opb) EMAC_STACR_OPBC(opb)
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#define EMAC4_STACR_BASE(opb) 0x00000000
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#define EMAC_STACR_PCDA_MASK 0x1f
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#define EMAC_STACR_PCDA_SHIFT 5
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#define EMAC_STACR_PRA_MASK 0x1f
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#define EMACX_STACR_STAC_MASK 0x00003800
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#define EMACX_STACR_STAC_READ 0x00001000
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#define EMACX_STACR_STAC_WRITE 0x00000800
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#define EMACX_STACR_STAC_IND_ADDR 0x00002000
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#define EMACX_STACR_STAC_IND_READ 0x00003800
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#define EMACX_STACR_STAC_IND_READINC 0x00003000
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#define EMACX_STACR_STAC_IND_WRITE 0x00002800
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/* EMACx_TRTR */
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#define EMAC_TRTR_SHIFT_EMAC4 24
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#define EMAC_TRTR_SHIFT 27
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/* EMAC specific TX descriptor control fields (write access) */
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#define EMAC_TX_CTRL_GFCS 0x0200
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#define EMAC_TX_CTRL_GP 0x0100
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#define EMAC_TX_CTRL_ISA 0x0080
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#define EMAC_TX_CTRL_RSA 0x0040
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#define EMAC_TX_CTRL_IVT 0x0020
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#define EMAC_TX_CTRL_RVT 0x0010
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#define EMAC_TX_CTRL_TAH_CSUM 0x000e
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/* EMAC specific TX descriptor status fields (read access) */
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#define EMAC_TX_ST_BFCS 0x0200
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#define EMAC_TX_ST_LCS 0x0080
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#define EMAC_TX_ST_ED 0x0040
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#define EMAC_TX_ST_EC 0x0020
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#define EMAC_TX_ST_LC 0x0010
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#define EMAC_TX_ST_MC 0x0008
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#define EMAC_TX_ST_SC 0x0004
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#define EMAC_TX_ST_UR 0x0002
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#define EMAC_TX_ST_SQE 0x0001
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#define EMAC_IS_BAD_TX (EMAC_TX_ST_LCS | EMAC_TX_ST_ED | \
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EMAC_TX_ST_EC | EMAC_TX_ST_LC | \
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EMAC_TX_ST_MC | EMAC_TX_ST_UR)
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#define EMAC_IS_BAD_TX_TAH (EMAC_TX_ST_LCS | EMAC_TX_ST_ED | \
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EMAC_TX_ST_EC | EMAC_TX_ST_LC)
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/* EMAC specific RX descriptor status fields (read access) */
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#define EMAC_RX_ST_OE 0x0200
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#define EMAC_RX_ST_PP 0x0100
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#define EMAC_RX_ST_BP 0x0080
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#define EMAC_RX_ST_RP 0x0040
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#define EMAC_RX_ST_SE 0x0020
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#define EMAC_RX_ST_AE 0x0010
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#define EMAC_RX_ST_BFCS 0x0008
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#define EMAC_RX_ST_PTL 0x0004
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#define EMAC_RX_ST_ORE 0x0002
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#define EMAC_RX_ST_IRE 0x0001
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#define EMAC_RX_TAH_BAD_CSUM 0x0003
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#define EMAC_BAD_RX_MASK (EMAC_RX_ST_OE | EMAC_RX_ST_BP | \
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EMAC_RX_ST_RP | EMAC_RX_ST_SE | \
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EMAC_RX_ST_AE | EMAC_RX_ST_BFCS | \
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EMAC_RX_ST_PTL | EMAC_RX_ST_ORE | \
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EMAC_RX_ST_IRE )
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#endif /* __IBM_NEWEMAC_H */
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