568 lines
16 KiB
C
568 lines
16 KiB
C
/* bnx2x_init.h: Broadcom Everest network driver.
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* Structures and macroes needed during the initialization.
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*
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* Copyright (c) 2007-2012 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation.
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*
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* Maintained by: Eilon Greenstein <eilong@broadcom.com>
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* Written by: Eliezer Tamir
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* Modified by: Vladislav Zolotarov <vladz@broadcom.com>
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*/
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#ifndef BNX2X_INIT_H
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#define BNX2X_INIT_H
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/* Init operation types and structures */
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enum {
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OP_RD = 0x1, /* read a single register */
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OP_WR, /* write a single register */
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OP_SW, /* copy a string to the device */
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OP_ZR, /* clear memory */
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OP_ZP, /* unzip then copy with DMAE */
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OP_WR_64, /* write 64 bit pattern */
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OP_WB, /* copy a string using DMAE */
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OP_WB_ZR, /* Clear a string using DMAE or indirect-wr */
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/* Skip the following ops if all of the init modes don't match */
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OP_IF_MODE_OR,
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/* Skip the following ops if any of the init modes don't match */
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OP_IF_MODE_AND,
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OP_MAX
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};
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enum {
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STAGE_START,
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STAGE_END,
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};
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/* Returns the index of start or end of a specific block stage in ops array*/
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#define BLOCK_OPS_IDX(block, stage, end) \
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(2*(((block)*NUM_OF_INIT_PHASES) + (stage)) + (end))
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/* structs for the various opcodes */
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struct raw_op {
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u32 op:8;
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u32 offset:24;
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u32 raw_data;
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};
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struct op_read {
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u32 op:8;
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u32 offset:24;
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u32 val;
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};
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struct op_write {
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u32 op:8;
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u32 offset:24;
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u32 val;
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};
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struct op_arr_write {
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u32 op:8;
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u32 offset:24;
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#ifdef __BIG_ENDIAN
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u16 data_len;
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u16 data_off;
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#else /* __LITTLE_ENDIAN */
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u16 data_off;
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u16 data_len;
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#endif
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};
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struct op_zero {
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u32 op:8;
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u32 offset:24;
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u32 len;
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};
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struct op_if_mode {
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u32 op:8;
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u32 cmd_offset:24;
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u32 mode_bit_map;
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};
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union init_op {
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struct op_read read;
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struct op_write write;
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struct op_arr_write arr_wr;
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struct op_zero zero;
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struct raw_op raw;
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struct op_if_mode if_mode;
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};
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/* Init Phases */
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enum {
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PHASE_COMMON,
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PHASE_PORT0,
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PHASE_PORT1,
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PHASE_PF0,
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PHASE_PF1,
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PHASE_PF2,
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PHASE_PF3,
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PHASE_PF4,
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PHASE_PF5,
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PHASE_PF6,
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PHASE_PF7,
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NUM_OF_INIT_PHASES
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};
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/* Init Modes */
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enum {
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MODE_ASIC = 0x00000001,
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MODE_FPGA = 0x00000002,
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MODE_EMUL = 0x00000004,
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MODE_E2 = 0x00000008,
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MODE_E3 = 0x00000010,
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MODE_PORT2 = 0x00000020,
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MODE_PORT4 = 0x00000040,
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MODE_SF = 0x00000080,
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MODE_MF = 0x00000100,
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MODE_MF_SD = 0x00000200,
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MODE_MF_SI = 0x00000400,
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MODE_MF_NIV = 0x00000800,
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MODE_E3_A0 = 0x00001000,
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MODE_E3_B0 = 0x00002000,
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MODE_COS3 = 0x00004000,
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MODE_COS6 = 0x00008000,
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MODE_LITTLE_ENDIAN = 0x00010000,
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MODE_BIG_ENDIAN = 0x00020000,
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};
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/* Init Blocks */
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enum {
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BLOCK_ATC,
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BLOCK_BRB1,
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BLOCK_CCM,
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BLOCK_CDU,
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BLOCK_CFC,
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BLOCK_CSDM,
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BLOCK_CSEM,
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BLOCK_DBG,
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BLOCK_DMAE,
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BLOCK_DORQ,
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BLOCK_HC,
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BLOCK_IGU,
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BLOCK_MISC,
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BLOCK_NIG,
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BLOCK_PBF,
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BLOCK_PGLUE_B,
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BLOCK_PRS,
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BLOCK_PXP2,
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BLOCK_PXP,
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BLOCK_QM,
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BLOCK_SRC,
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BLOCK_TCM,
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BLOCK_TM,
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BLOCK_TSDM,
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BLOCK_TSEM,
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BLOCK_UCM,
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BLOCK_UPB,
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BLOCK_USDM,
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BLOCK_USEM,
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BLOCK_XCM,
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BLOCK_XPB,
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BLOCK_XSDM,
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BLOCK_XSEM,
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BLOCK_MISC_AEU,
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NUM_OF_INIT_BLOCKS
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};
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/* QM queue numbers */
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#define BNX2X_ETH_Q 0
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#define BNX2X_TOE_Q 3
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#define BNX2X_TOE_ACK_Q 6
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#define BNX2X_ISCSI_Q 9
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#define BNX2X_ISCSI_ACK_Q 11
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#define BNX2X_FCOE_Q 10
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/* Vnics per mode */
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#define BNX2X_PORT2_MODE_NUM_VNICS 4
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#define BNX2X_PORT4_MODE_NUM_VNICS 2
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/* COS offset for port1 in E3 B0 4port mode */
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#define BNX2X_E3B0_PORT1_COS_OFFSET 3
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/* QM Register addresses */
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#define BNX2X_Q_VOQ_REG_ADDR(pf_q_num)\
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(QM_REG_QVOQIDX_0 + 4 * (pf_q_num))
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#define BNX2X_VOQ_Q_REG_ADDR(cos, pf_q_num)\
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(QM_REG_VOQQMASK_0_LSB + 4 * ((cos) * 2 + ((pf_q_num) >> 5)))
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#define BNX2X_Q_CMDQ_REG_ADDR(pf_q_num)\
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(QM_REG_BYTECRDCMDQ_0 + 4 * ((pf_q_num) >> 4))
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/* extracts the QM queue number for the specified port and vnic */
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#define BNX2X_PF_Q_NUM(q_num, port, vnic)\
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((((port) << 1) | (vnic)) * 16 + (q_num))
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/* Maps the specified queue to the specified COS */
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static inline void bnx2x_map_q_cos(struct bnx2x *bp, u32 q_num, u32 new_cos)
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{
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/* find current COS mapping */
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u32 curr_cos = REG_RD(bp, QM_REG_QVOQIDX_0 + q_num * 4);
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/* check if queue->COS mapping has changed */
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if (curr_cos != new_cos) {
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u32 num_vnics = BNX2X_PORT2_MODE_NUM_VNICS;
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u32 reg_addr, reg_bit_map, vnic;
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/* update parameters for 4port mode */
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if (INIT_MODE_FLAGS(bp) & MODE_PORT4) {
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num_vnics = BNX2X_PORT4_MODE_NUM_VNICS;
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if (BP_PORT(bp)) {
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curr_cos += BNX2X_E3B0_PORT1_COS_OFFSET;
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new_cos += BNX2X_E3B0_PORT1_COS_OFFSET;
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}
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}
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/* change queue mapping for each VNIC */
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for (vnic = 0; vnic < num_vnics; vnic++) {
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u32 pf_q_num =
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BNX2X_PF_Q_NUM(q_num, BP_PORT(bp), vnic);
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u32 q_bit_map = 1 << (pf_q_num & 0x1f);
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/* overwrite queue->VOQ mapping */
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REG_WR(bp, BNX2X_Q_VOQ_REG_ADDR(pf_q_num), new_cos);
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/* clear queue bit from current COS bit map */
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reg_addr = BNX2X_VOQ_Q_REG_ADDR(curr_cos, pf_q_num);
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reg_bit_map = REG_RD(bp, reg_addr);
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REG_WR(bp, reg_addr, reg_bit_map & (~q_bit_map));
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/* set queue bit in new COS bit map */
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reg_addr = BNX2X_VOQ_Q_REG_ADDR(new_cos, pf_q_num);
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reg_bit_map = REG_RD(bp, reg_addr);
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REG_WR(bp, reg_addr, reg_bit_map | q_bit_map);
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/* set/clear queue bit in command-queue bit map
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(E2/E3A0 only, valid COS values are 0/1) */
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if (!(INIT_MODE_FLAGS(bp) & MODE_E3_B0)) {
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reg_addr = BNX2X_Q_CMDQ_REG_ADDR(pf_q_num);
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reg_bit_map = REG_RD(bp, reg_addr);
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q_bit_map = 1 << (2 * (pf_q_num & 0xf));
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reg_bit_map = new_cos ?
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(reg_bit_map | q_bit_map) :
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(reg_bit_map & (~q_bit_map));
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REG_WR(bp, reg_addr, reg_bit_map);
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}
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}
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}
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}
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/* Configures the QM according to the specified per-traffic-type COSes */
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static inline void bnx2x_dcb_config_qm(struct bnx2x *bp, enum cos_mode mode,
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struct priority_cos *traffic_cos)
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{
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bnx2x_map_q_cos(bp, BNX2X_FCOE_Q,
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traffic_cos[LLFC_TRAFFIC_TYPE_FCOE].cos);
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bnx2x_map_q_cos(bp, BNX2X_ISCSI_Q,
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traffic_cos[LLFC_TRAFFIC_TYPE_ISCSI].cos);
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bnx2x_map_q_cos(bp, BNX2X_ISCSI_ACK_Q,
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traffic_cos[LLFC_TRAFFIC_TYPE_ISCSI].cos);
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if (mode != STATIC_COS) {
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/* required only in backward compatible COS mode */
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bnx2x_map_q_cos(bp, BNX2X_ETH_Q,
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traffic_cos[LLFC_TRAFFIC_TYPE_NW].cos);
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bnx2x_map_q_cos(bp, BNX2X_TOE_Q,
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traffic_cos[LLFC_TRAFFIC_TYPE_NW].cos);
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bnx2x_map_q_cos(bp, BNX2X_TOE_ACK_Q,
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traffic_cos[LLFC_TRAFFIC_TYPE_NW].cos);
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}
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}
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/* Returns the index of start or end of a specific block stage in ops array*/
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#define BLOCK_OPS_IDX(block, stage, end) \
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(2*(((block)*NUM_OF_INIT_PHASES) + (stage)) + (end))
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#define INITOP_SET 0 /* set the HW directly */
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#define INITOP_CLEAR 1 /* clear the HW directly */
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#define INITOP_INIT 2 /* set the init-value array */
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/****************************************************************************
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* ILT management
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****************************************************************************/
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struct ilt_line {
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dma_addr_t page_mapping;
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void *page;
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u32 size;
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};
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struct ilt_client_info {
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u32 page_size;
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u16 start;
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u16 end;
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u16 client_num;
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u16 flags;
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#define ILT_CLIENT_SKIP_INIT 0x1
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#define ILT_CLIENT_SKIP_MEM 0x2
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};
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struct bnx2x_ilt {
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u32 start_line;
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struct ilt_line *lines;
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struct ilt_client_info clients[4];
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#define ILT_CLIENT_CDU 0
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#define ILT_CLIENT_QM 1
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#define ILT_CLIENT_SRC 2
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#define ILT_CLIENT_TM 3
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};
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/****************************************************************************
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* SRC configuration
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****************************************************************************/
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struct src_ent {
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u8 opaque[56];
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u64 next;
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};
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/****************************************************************************
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* Parity configuration
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****************************************************************************/
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#define BLOCK_PRTY_INFO(block, en_mask, m1, m1h, m2, m3) \
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{ \
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block##_REG_##block##_PRTY_MASK, \
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block##_REG_##block##_PRTY_STS_CLR, \
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en_mask, {m1, m1h, m2, m3}, #block \
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}
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#define BLOCK_PRTY_INFO_0(block, en_mask, m1, m1h, m2, m3) \
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{ \
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block##_REG_##block##_PRTY_MASK_0, \
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block##_REG_##block##_PRTY_STS_CLR_0, \
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en_mask, {m1, m1h, m2, m3}, #block"_0" \
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}
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#define BLOCK_PRTY_INFO_1(block, en_mask, m1, m1h, m2, m3) \
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{ \
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block##_REG_##block##_PRTY_MASK_1, \
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block##_REG_##block##_PRTY_STS_CLR_1, \
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en_mask, {m1, m1h, m2, m3}, #block"_1" \
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}
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static const struct {
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u32 mask_addr;
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u32 sts_clr_addr;
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u32 en_mask; /* Mask to enable parity attentions */
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struct {
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u32 e1; /* 57710 */
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u32 e1h; /* 57711 */
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u32 e2; /* 57712 */
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u32 e3; /* 578xx */
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} reg_mask; /* Register mask (all valid bits) */
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char name[7]; /* Block's longest name is 6 characters long
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* (name + suffix)
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*/
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} bnx2x_blocks_parity_data[] = {
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/* bit 19 masked */
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/* REG_WR(bp, PXP_REG_PXP_PRTY_MASK, 0x80000); */
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/* bit 5,18,20-31 */
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/* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_0, 0xfff40020); */
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/* bit 5 */
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/* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_1, 0x20); */
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/* REG_WR(bp, HC_REG_HC_PRTY_MASK, 0x0); */
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/* REG_WR(bp, MISC_REG_MISC_PRTY_MASK, 0x0); */
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/* Block IGU, MISC, PXP and PXP2 parity errors as long as we don't
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* want to handle "system kill" flow at the moment.
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*/
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BLOCK_PRTY_INFO(PXP, 0x7ffffff, 0x3ffffff, 0x3ffffff, 0x7ffffff,
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0x7ffffff),
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BLOCK_PRTY_INFO_0(PXP2, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
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0xffffffff),
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BLOCK_PRTY_INFO_1(PXP2, 0x1ffffff, 0x7f, 0x7f, 0x7ff, 0x1ffffff),
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BLOCK_PRTY_INFO(HC, 0x7, 0x7, 0x7, 0, 0),
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BLOCK_PRTY_INFO(NIG, 0xffffffff, 0x3fffffff, 0xffffffff, 0, 0),
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BLOCK_PRTY_INFO_0(NIG, 0xffffffff, 0, 0, 0xffffffff, 0xffffffff),
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BLOCK_PRTY_INFO_1(NIG, 0xffff, 0, 0, 0xff, 0xffff),
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BLOCK_PRTY_INFO(IGU, 0x7ff, 0, 0, 0x7ff, 0x7ff),
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BLOCK_PRTY_INFO(MISC, 0x1, 0x1, 0x1, 0x1, 0x1),
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BLOCK_PRTY_INFO(QM, 0, 0x1ff, 0xfff, 0xfff, 0xfff),
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BLOCK_PRTY_INFO(ATC, 0x1f, 0, 0, 0x1f, 0x1f),
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BLOCK_PRTY_INFO(PGLUE_B, 0x3, 0, 0, 0x3, 0x3),
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BLOCK_PRTY_INFO(DORQ, 0, 0x3, 0x3, 0x3, 0x3),
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{GRCBASE_UPB + PB_REG_PB_PRTY_MASK,
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GRCBASE_UPB + PB_REG_PB_PRTY_STS_CLR, 0xf,
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{0xf, 0xf, 0xf, 0xf}, "UPB"},
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{GRCBASE_XPB + PB_REG_PB_PRTY_MASK,
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GRCBASE_XPB + PB_REG_PB_PRTY_STS_CLR, 0,
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{0xf, 0xf, 0xf, 0xf}, "XPB"},
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BLOCK_PRTY_INFO(SRC, 0x4, 0x7, 0x7, 0x7, 0x7),
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BLOCK_PRTY_INFO(CDU, 0, 0x1f, 0x1f, 0x1f, 0x1f),
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BLOCK_PRTY_INFO(CFC, 0, 0xf, 0xf, 0xf, 0x3f),
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BLOCK_PRTY_INFO(DBG, 0, 0x1, 0x1, 0x1, 0x1),
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BLOCK_PRTY_INFO(DMAE, 0, 0xf, 0xf, 0xf, 0xf),
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BLOCK_PRTY_INFO(BRB1, 0, 0xf, 0xf, 0xf, 0xf),
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BLOCK_PRTY_INFO(PRS, (1<<6), 0xff, 0xff, 0xff, 0xff),
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BLOCK_PRTY_INFO(PBF, 0, 0, 0x3ffff, 0xfffff, 0xfffffff),
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BLOCK_PRTY_INFO(TM, 0, 0, 0x7f, 0x7f, 0x7f),
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BLOCK_PRTY_INFO(TSDM, 0x18, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
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BLOCK_PRTY_INFO(CSDM, 0x8, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
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BLOCK_PRTY_INFO(USDM, 0x38, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
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BLOCK_PRTY_INFO(XSDM, 0x8, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
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BLOCK_PRTY_INFO(TCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
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BLOCK_PRTY_INFO(CCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
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BLOCK_PRTY_INFO(UCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
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BLOCK_PRTY_INFO(XCM, 0, 0, 0x3fffffff, 0x3fffffff, 0x3fffffff),
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BLOCK_PRTY_INFO_0(TSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
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0xffffffff),
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BLOCK_PRTY_INFO_1(TSEM, 0, 0x3, 0x1f, 0x3f, 0x3f),
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BLOCK_PRTY_INFO_0(USEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
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0xffffffff),
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BLOCK_PRTY_INFO_1(USEM, 0, 0x3, 0x1f, 0x1f, 0x1f),
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BLOCK_PRTY_INFO_0(CSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
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0xffffffff),
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BLOCK_PRTY_INFO_1(CSEM, 0, 0x3, 0x1f, 0x1f, 0x1f),
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BLOCK_PRTY_INFO_0(XSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
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0xffffffff),
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BLOCK_PRTY_INFO_1(XSEM, 0, 0x3, 0x1f, 0x3f, 0x3f),
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};
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/* [28] MCP Latched rom_parity
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* [29] MCP Latched ump_rx_parity
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* [30] MCP Latched ump_tx_parity
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* [31] MCP Latched scpad_parity
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*/
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#define MISC_AEU_ENABLE_MCP_PRTY_BITS \
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(AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
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AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
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AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
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AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
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/* Below registers control the MCP parity attention output. When
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* MISC_AEU_ENABLE_MCP_PRTY_BITS are set - attentions are
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* enabled, when cleared - disabled.
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*/
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static const u32 mcp_attn_ctl_regs[] = {
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MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0,
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MISC_REG_AEU_ENABLE4_NIG_0,
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MISC_REG_AEU_ENABLE4_PXP_0,
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MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0,
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MISC_REG_AEU_ENABLE4_NIG_1,
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MISC_REG_AEU_ENABLE4_PXP_1
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};
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static inline void bnx2x_set_mcp_parity(struct bnx2x *bp, u8 enable)
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{
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int i;
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u32 reg_val;
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for (i = 0; i < ARRAY_SIZE(mcp_attn_ctl_regs); i++) {
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reg_val = REG_RD(bp, mcp_attn_ctl_regs[i]);
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if (enable)
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reg_val |= MISC_AEU_ENABLE_MCP_PRTY_BITS;
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else
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reg_val &= ~MISC_AEU_ENABLE_MCP_PRTY_BITS;
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REG_WR(bp, mcp_attn_ctl_regs[i], reg_val);
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}
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}
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static inline u32 bnx2x_parity_reg_mask(struct bnx2x *bp, int idx)
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{
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if (CHIP_IS_E1(bp))
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return bnx2x_blocks_parity_data[idx].reg_mask.e1;
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else if (CHIP_IS_E1H(bp))
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return bnx2x_blocks_parity_data[idx].reg_mask.e1h;
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else if (CHIP_IS_E2(bp))
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return bnx2x_blocks_parity_data[idx].reg_mask.e2;
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else /* CHIP_IS_E3 */
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return bnx2x_blocks_parity_data[idx].reg_mask.e3;
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}
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static inline void bnx2x_disable_blocks_parity(struct bnx2x *bp)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(bnx2x_blocks_parity_data); i++) {
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u32 dis_mask = bnx2x_parity_reg_mask(bp, i);
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if (dis_mask) {
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REG_WR(bp, bnx2x_blocks_parity_data[i].mask_addr,
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dis_mask);
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DP(NETIF_MSG_HW, "Setting parity mask "
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"for %s to\t\t0x%x\n",
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bnx2x_blocks_parity_data[i].name, dis_mask);
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}
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}
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/* Disable MCP parity attentions */
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bnx2x_set_mcp_parity(bp, false);
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}
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/**
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* Clear the parity error status registers.
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*/
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static inline void bnx2x_clear_blocks_parity(struct bnx2x *bp)
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{
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int i;
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u32 reg_val, mcp_aeu_bits =
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AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY |
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AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY |
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AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY |
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AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY;
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/* Clear SEM_FAST parities */
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REG_WR(bp, XSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
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REG_WR(bp, TSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
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REG_WR(bp, USEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
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REG_WR(bp, CSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
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for (i = 0; i < ARRAY_SIZE(bnx2x_blocks_parity_data); i++) {
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u32 reg_mask = bnx2x_parity_reg_mask(bp, i);
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if (reg_mask) {
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reg_val = REG_RD(bp, bnx2x_blocks_parity_data[i].
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sts_clr_addr);
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if (reg_val & reg_mask)
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DP(NETIF_MSG_HW,
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"Parity errors in %s: 0x%x\n",
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bnx2x_blocks_parity_data[i].name,
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reg_val & reg_mask);
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}
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}
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/* Check if there were parity attentions in MCP */
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reg_val = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_MCP);
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if (reg_val & mcp_aeu_bits)
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DP(NETIF_MSG_HW, "Parity error in MCP: 0x%x\n",
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reg_val & mcp_aeu_bits);
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/* Clear parity attentions in MCP:
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* [7] clears Latched rom_parity
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* [8] clears Latched ump_rx_parity
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* [9] clears Latched ump_tx_parity
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* [10] clears Latched scpad_parity (both ports)
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*/
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REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x780);
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}
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static inline void bnx2x_enable_blocks_parity(struct bnx2x *bp)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(bnx2x_blocks_parity_data); i++) {
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u32 reg_mask = bnx2x_parity_reg_mask(bp, i);
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if (reg_mask)
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REG_WR(bp, bnx2x_blocks_parity_data[i].mask_addr,
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bnx2x_blocks_parity_data[i].en_mask & reg_mask);
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}
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/* Enable MCP parity attentions */
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bnx2x_set_mcp_parity(bp, true);
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}
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#endif /* BNX2X_INIT_H */
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