351 lines
8.2 KiB
C
351 lines
8.2 KiB
C
/*
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* MPC85xx RDB Board Setup
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*
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* Copyright 2009,2012 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/kdev_t.h>
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#include <linux/delay.h>
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#include <linux/seq_file.h>
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#include <linux/interrupt.h>
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#include <linux/of_platform.h>
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#include <asm/time.h>
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#include <asm/machdep.h>
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#include <asm/pci-bridge.h>
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#include <mm/mmu_decl.h>
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#include <asm/prom.h>
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#include <asm/udbg.h>
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#include <asm/mpic.h>
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#include <asm/qe.h>
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#include <asm/qe_ic.h>
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#include <asm/fsl_guts.h>
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#include <sysdev/fsl_soc.h>
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#include <sysdev/fsl_pci.h>
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#include "smp.h"
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#include "mpc85xx.h"
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#undef DEBUG
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#ifdef DEBUG
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#define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args)
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#else
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#define DBG(fmt, args...)
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#endif
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void __init mpc85xx_rdb_pic_init(void)
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{
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struct mpic *mpic;
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unsigned long root = of_get_flat_dt_root();
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#ifdef CONFIG_QUICC_ENGINE
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struct device_node *np;
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#endif
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if (of_flat_dt_is_compatible(root, "fsl,MPC85XXRDB-CAMP")) {
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mpic = mpic_alloc(NULL, 0, MPIC_NO_RESET |
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MPIC_BIG_ENDIAN |
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MPIC_SINGLE_DEST_CPU,
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0, 256, " OpenPIC ");
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} else {
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mpic = mpic_alloc(NULL, 0,
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MPIC_BIG_ENDIAN |
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MPIC_SINGLE_DEST_CPU,
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0, 256, " OpenPIC ");
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}
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BUG_ON(mpic == NULL);
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mpic_init(mpic);
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#ifdef CONFIG_QUICC_ENGINE
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np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
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if (np) {
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qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
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qe_ic_cascade_high_mpic);
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of_node_put(np);
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} else
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pr_err("%s: Could not find qe-ic node\n", __func__);
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#endif
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}
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/*
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* Setup the architecture
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*/
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static void __init mpc85xx_rdb_setup_arch(void)
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{
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#if defined(CONFIG_PCI) || defined(CONFIG_QUICC_ENGINE)
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struct device_node *np;
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#endif
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if (ppc_md.progress)
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ppc_md.progress("mpc85xx_rdb_setup_arch()", 0);
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#ifdef CONFIG_PCI
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for_each_node_by_type(np, "pci") {
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if (of_device_is_compatible(np, "fsl,mpc8548-pcie"))
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fsl_add_bridge(np, 0);
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}
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#endif
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mpc85xx_smp_init();
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#ifdef CONFIG_QUICC_ENGINE
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np = of_find_compatible_node(NULL, NULL, "fsl,qe");
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if (!np) {
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pr_err("%s: Could not find Quicc Engine node\n", __func__);
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goto qe_fail;
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}
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qe_reset();
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of_node_put(np);
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np = of_find_node_by_name(NULL, "par_io");
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if (np) {
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struct device_node *ucc;
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par_io_init(np);
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of_node_put(np);
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for_each_node_by_name(ucc, "ucc")
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par_io_of_config(ucc);
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}
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#if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE)
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if (machine_is(p1025_rdb)) {
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struct ccsr_guts __iomem *guts;
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np = of_find_node_by_name(NULL, "global-utilities");
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if (np) {
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guts = of_iomap(np, 0);
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if (!guts) {
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pr_err("mpc85xx-rdb: could not map global utilities register\n");
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} else {
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/* P1025 has pins muxed for QE and other functions. To
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* enable QE UEC mode, we need to set bit QE0 for UCC1
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* in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
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* and QE12 for QE MII management singals in PMUXCR
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* register.
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*/
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setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
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MPC85xx_PMUXCR_QE(3) |
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MPC85xx_PMUXCR_QE(9) |
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MPC85xx_PMUXCR_QE(12));
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iounmap(guts);
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}
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of_node_put(np);
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}
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}
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#endif
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qe_fail:
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#endif /* CONFIG_QUICC_ENGINE */
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printk(KERN_INFO "MPC85xx RDB board from Freescale Semiconductor\n");
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}
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machine_device_initcall(p2020_rdb, mpc85xx_common_publish_devices);
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machine_device_initcall(p2020_rdb_pc, mpc85xx_common_publish_devices);
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machine_device_initcall(p1020_mbg_pc, mpc85xx_common_publish_devices);
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machine_device_initcall(p1020_rdb, mpc85xx_common_publish_devices);
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machine_device_initcall(p1020_rdb_pc, mpc85xx_common_publish_devices);
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machine_device_initcall(p1020_utm_pc, mpc85xx_common_publish_devices);
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machine_device_initcall(p1021_rdb_pc, mpc85xx_common_publish_devices);
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machine_device_initcall(p1025_rdb, mpc85xx_common_publish_devices);
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/*
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* Called very early, device-tree isn't unflattened
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*/
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static int __init p2020_rdb_probe(void)
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{
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unsigned long root = of_get_flat_dt_root();
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if (of_flat_dt_is_compatible(root, "fsl,P2020RDB"))
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return 1;
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return 0;
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}
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static int __init p1020_rdb_probe(void)
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{
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unsigned long root = of_get_flat_dt_root();
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if (of_flat_dt_is_compatible(root, "fsl,P1020RDB"))
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return 1;
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return 0;
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}
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static int __init p1020_rdb_pc_probe(void)
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{
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unsigned long root = of_get_flat_dt_root();
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return of_flat_dt_is_compatible(root, "fsl,P1020RDB-PC");
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}
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static int __init p1021_rdb_pc_probe(void)
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{
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unsigned long root = of_get_flat_dt_root();
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if (of_flat_dt_is_compatible(root, "fsl,P1021RDB-PC"))
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return 1;
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return 0;
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}
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static int __init p2020_rdb_pc_probe(void)
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{
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unsigned long root = of_get_flat_dt_root();
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if (of_flat_dt_is_compatible(root, "fsl,P2020RDB-PC"))
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return 1;
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return 0;
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}
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static int __init p1025_rdb_probe(void)
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{
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unsigned long root = of_get_flat_dt_root();
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return of_flat_dt_is_compatible(root, "fsl,P1025RDB");
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}
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static int __init p1020_mbg_pc_probe(void)
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{
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unsigned long root = of_get_flat_dt_root();
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return of_flat_dt_is_compatible(root, "fsl,P1020MBG-PC");
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}
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static int __init p1020_utm_pc_probe(void)
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{
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unsigned long root = of_get_flat_dt_root();
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return of_flat_dt_is_compatible(root, "fsl,P1020UTM-PC");
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}
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define_machine(p2020_rdb) {
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.name = "P2020 RDB",
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.probe = p2020_rdb_probe,
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.setup_arch = mpc85xx_rdb_setup_arch,
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.init_IRQ = mpc85xx_rdb_pic_init,
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#ifdef CONFIG_PCI
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.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
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#endif
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.get_irq = mpic_get_irq,
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.restart = fsl_rstcr_restart,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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};
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define_machine(p1020_rdb) {
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.name = "P1020 RDB",
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.probe = p1020_rdb_probe,
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.setup_arch = mpc85xx_rdb_setup_arch,
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.init_IRQ = mpc85xx_rdb_pic_init,
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#ifdef CONFIG_PCI
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.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
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#endif
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.get_irq = mpic_get_irq,
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.restart = fsl_rstcr_restart,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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};
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define_machine(p1021_rdb_pc) {
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.name = "P1021 RDB-PC",
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.probe = p1021_rdb_pc_probe,
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.setup_arch = mpc85xx_rdb_setup_arch,
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.init_IRQ = mpc85xx_rdb_pic_init,
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#ifdef CONFIG_PCI
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.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
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#endif
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.get_irq = mpic_get_irq,
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.restart = fsl_rstcr_restart,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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};
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define_machine(p2020_rdb_pc) {
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.name = "P2020RDB-PC",
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.probe = p2020_rdb_pc_probe,
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.setup_arch = mpc85xx_rdb_setup_arch,
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.init_IRQ = mpc85xx_rdb_pic_init,
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#ifdef CONFIG_PCI
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.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
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#endif
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.get_irq = mpic_get_irq,
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.restart = fsl_rstcr_restart,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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};
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define_machine(p1025_rdb) {
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.name = "P1025 RDB",
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.probe = p1025_rdb_probe,
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.setup_arch = mpc85xx_rdb_setup_arch,
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.init_IRQ = mpc85xx_rdb_pic_init,
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#ifdef CONFIG_PCI
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.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
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#endif
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.get_irq = mpic_get_irq,
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.restart = fsl_rstcr_restart,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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};
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define_machine(p1020_mbg_pc) {
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.name = "P1020 MBG-PC",
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.probe = p1020_mbg_pc_probe,
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.setup_arch = mpc85xx_rdb_setup_arch,
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.init_IRQ = mpc85xx_rdb_pic_init,
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#ifdef CONFIG_PCI
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.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
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#endif
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.get_irq = mpic_get_irq,
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.restart = fsl_rstcr_restart,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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};
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define_machine(p1020_utm_pc) {
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.name = "P1020 UTM-PC",
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.probe = p1020_utm_pc_probe,
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.setup_arch = mpc85xx_rdb_setup_arch,
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.init_IRQ = mpc85xx_rdb_pic_init,
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#ifdef CONFIG_PCI
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.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
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#endif
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.get_irq = mpic_get_irq,
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.restart = fsl_rstcr_restart,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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};
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define_machine(p1020_rdb_pc) {
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.name = "P1020RDB-PC",
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.probe = p1020_rdb_pc_probe,
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.setup_arch = mpc85xx_rdb_setup_arch,
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.init_IRQ = mpc85xx_rdb_pic_init,
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#ifdef CONFIG_PCI
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.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
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#endif
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.get_irq = mpic_get_irq,
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.restart = fsl_rstcr_restart,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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};
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