224 lines
5.9 KiB
C
224 lines
5.9 KiB
C
/*
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* Copyright (C) 2004 IBM
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*
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* Implements the generic device dma API for powerpc.
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* the pci and vio busses
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*/
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#ifndef _ASM_DMA_MAPPING_H
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#define _ASM_DMA_MAPPING_H
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#ifdef __KERNEL__
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#include <linux/types.h>
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#include <linux/cache.h>
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/* need struct page definitions */
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#include <linux/mm.h>
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#include <linux/scatterlist.h>
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#include <linux/dma-attrs.h>
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#include <linux/dma-debug.h>
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#include <asm/io.h>
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#include <asm/swiotlb.h>
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#define DMA_ERROR_CODE (~(dma_addr_t)0x0)
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/* Some dma direct funcs must be visible for use in other dma_ops */
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extern void *dma_direct_alloc_coherent(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t flag,
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struct dma_attrs *attrs);
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extern void dma_direct_free_coherent(struct device *dev, size_t size,
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void *vaddr, dma_addr_t dma_handle,
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struct dma_attrs *attrs);
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#ifdef CONFIG_NOT_COHERENT_CACHE
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/*
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* DMA-consistent mapping functions for PowerPCs that don't support
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* cache snooping. These allocate/free a region of uncached mapped
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* memory space for use with DMA devices. Alternatively, you could
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* allocate the space "normally" and use the cache management functions
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* to ensure it is consistent.
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*/
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struct device;
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extern void *__dma_alloc_coherent(struct device *dev, size_t size,
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dma_addr_t *handle, gfp_t gfp);
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extern void __dma_free_coherent(size_t size, void *vaddr);
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extern void __dma_sync(void *vaddr, size_t size, int direction);
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extern void __dma_sync_page(struct page *page, unsigned long offset,
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size_t size, int direction);
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extern unsigned long __dma_get_coherent_pfn(unsigned long cpu_addr);
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#else /* ! CONFIG_NOT_COHERENT_CACHE */
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/*
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* Cache coherent cores.
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*/
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#define __dma_alloc_coherent(dev, gfp, size, handle) NULL
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#define __dma_free_coherent(size, addr) ((void)0)
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#define __dma_sync(addr, size, rw) ((void)0)
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#define __dma_sync_page(pg, off, sz, rw) ((void)0)
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#endif /* ! CONFIG_NOT_COHERENT_CACHE */
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static inline unsigned long device_to_mask(struct device *dev)
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{
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if (dev->dma_mask && *dev->dma_mask)
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return *dev->dma_mask;
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/* Assume devices without mask can take 32 bit addresses */
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return 0xfffffffful;
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}
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/*
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* Available generic sets of operations
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*/
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#ifdef CONFIG_PPC64
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extern struct dma_map_ops dma_iommu_ops;
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#endif
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extern struct dma_map_ops dma_direct_ops;
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static inline struct dma_map_ops *get_dma_ops(struct device *dev)
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{
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/* We don't handle the NULL dev case for ISA for now. We could
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* do it via an out of line call but it is not needed for now. The
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* only ISA DMA device we support is the floppy and we have a hack
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* in the floppy driver directly to get a device for us.
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*/
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if (unlikely(dev == NULL))
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return NULL;
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return dev->archdata.dma_ops;
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}
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static inline void set_dma_ops(struct device *dev, struct dma_map_ops *ops)
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{
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dev->archdata.dma_ops = ops;
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}
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/*
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* get_dma_offset()
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*
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* Get the dma offset on configurations where the dma address can be determined
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* from the physical address by looking at a simple offset. Direct dma and
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* swiotlb use this function, but it is typically not used by implementations
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* with an iommu.
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*/
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static inline dma_addr_t get_dma_offset(struct device *dev)
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{
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if (dev)
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return dev->archdata.dma_data.dma_offset;
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return PCI_DRAM_OFFSET;
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}
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static inline void set_dma_offset(struct device *dev, dma_addr_t off)
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{
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if (dev)
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dev->archdata.dma_data.dma_offset = off;
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}
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/* this will be removed soon */
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#define flush_write_buffers()
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#include <asm-generic/dma-mapping-common.h>
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static inline int dma_supported(struct device *dev, u64 mask)
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{
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struct dma_map_ops *dma_ops = get_dma_ops(dev);
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if (unlikely(dma_ops == NULL))
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return 0;
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if (dma_ops->dma_supported == NULL)
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return 1;
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return dma_ops->dma_supported(dev, mask);
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}
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extern int dma_set_mask(struct device *dev, u64 dma_mask);
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#define dma_alloc_coherent(d,s,h,f) dma_alloc_attrs(d,s,h,f,NULL)
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static inline void *dma_alloc_attrs(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t flag,
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struct dma_attrs *attrs)
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{
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struct dma_map_ops *dma_ops = get_dma_ops(dev);
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void *cpu_addr;
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BUG_ON(!dma_ops);
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cpu_addr = dma_ops->alloc(dev, size, dma_handle, flag, attrs);
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debug_dma_alloc_coherent(dev, size, *dma_handle, cpu_addr);
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return cpu_addr;
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}
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#define dma_free_coherent(d,s,c,h) dma_free_attrs(d,s,c,h,NULL)
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static inline void dma_free_attrs(struct device *dev, size_t size,
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void *cpu_addr, dma_addr_t dma_handle,
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struct dma_attrs *attrs)
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{
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struct dma_map_ops *dma_ops = get_dma_ops(dev);
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BUG_ON(!dma_ops);
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debug_dma_free_coherent(dev, size, cpu_addr, dma_handle);
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dma_ops->free(dev, size, cpu_addr, dma_handle, attrs);
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}
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static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
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{
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struct dma_map_ops *dma_ops = get_dma_ops(dev);
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if (dma_ops->mapping_error)
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return dma_ops->mapping_error(dev, dma_addr);
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#ifdef CONFIG_PPC64
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return (dma_addr == DMA_ERROR_CODE);
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#else
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return 0;
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#endif
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}
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static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
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{
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#ifdef CONFIG_SWIOTLB
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struct dev_archdata *sd = &dev->archdata;
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if (sd->max_direct_dma_addr && addr + size > sd->max_direct_dma_addr)
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return 0;
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#endif
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if (!dev->dma_mask)
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return 0;
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return addr + size - 1 <= *dev->dma_mask;
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}
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static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
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{
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return paddr + get_dma_offset(dev);
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}
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static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr)
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{
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return daddr - get_dma_offset(dev);
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}
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#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
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#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
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extern int dma_mmap_coherent(struct device *, struct vm_area_struct *,
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void *, dma_addr_t, size_t);
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#define ARCH_HAS_DMA_MMAP_COHERENT
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static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
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enum dma_data_direction direction)
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{
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BUG_ON(direction == DMA_NONE);
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__dma_sync(vaddr, size, (int)direction);
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}
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#endif /* __KERNEL__ */
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#endif /* _ASM_DMA_MAPPING_H */
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