97 lines
3.2 KiB
Plaintext
97 lines
3.2 KiB
Plaintext
/*
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* P1021 RDB Device Tree Source (36-bit address map)
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*
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* Copyright 2011 Freescale Semiconductor Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/include/ "fsl/p1021si-pre.dtsi"
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/ {
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model = "fsl,P1021RDB";
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compatible = "fsl,P1021RDB-PC";
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memory {
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device_type = "memory";
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};
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lbc: localbus@fffe05000 {
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reg = <0xf 0xffe05000 0 0x1000>;
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/* NOR, NAND Flashes and Vitesse 5 port L2 switch */
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ranges = <0x0 0x0 0xf 0xef000000 0x01000000
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0x1 0x0 0xf 0xff800000 0x00040000
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0x2 0x0 0xf 0xffb00000 0x00020000>;
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};
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soc: soc@fffe00000 {
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ranges = <0x0 0xf 0xffe00000 0x100000>;
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};
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pci0: pcie@fffe09000 {
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ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
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reg = <0xf 0xffe09000 0 0x1000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0xa0000000
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0x2000000 0x0 0xa0000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x100000>;
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};
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};
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pci1: pcie@fffe0a000 {
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reg = <0xf 0xffe0a000 0 0x1000>;
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ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0xc0000000
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0x2000000 0x0 0xc0000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x100000>;
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};
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};
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qe: qe@fffe80000 {
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ranges = <0x0 0xf 0xffe80000 0x40000>;
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reg = <0xf 0xffe80000 0 0x480>;
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brg-frequency = <0>;
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bus-frequency = <0>;
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};
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};
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/include/ "p1021rdb.dtsi"
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/include/ "fsl/p1021si-post.dtsi"
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