361 lines
12 KiB
C
361 lines
12 KiB
C
/***********************license start***************
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* Author: Cavium Networks
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*
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* Contact: support@caviumnetworks.com
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* This file is part of the OCTEON SDK
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*
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* Copyright (c) 2003-2010 Cavium Networks
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful, but
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
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* NONINFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this file; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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* or visit http://www.gnu.org/licenses/.
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*
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* This file may also be available under a different license from Cavium.
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* Contact Cavium Networks for more information
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***********************license end**************************************/
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/*
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* Interface to the Level 2 Cache (L2C) control, measurement, and debugging
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* facilities.
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*/
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#ifndef __CVMX_L2C_H__
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#define __CVMX_L2C_H__
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#define CVMX_L2_ASSOC cvmx_l2c_get_num_assoc() /* Deprecated macro, use function */
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#define CVMX_L2_SET_BITS cvmx_l2c_get_set_bits() /* Deprecated macro, use function */
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#define CVMX_L2_SETS cvmx_l2c_get_num_sets() /* Deprecated macro, use function */
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#define CVMX_L2C_IDX_ADDR_SHIFT 7 /* based on 128 byte cache line size */
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#define CVMX_L2C_IDX_MASK (cvmx_l2c_get_num_sets() - 1)
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/* Defines for index aliasing computations */
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#define CVMX_L2C_TAG_ADDR_ALIAS_SHIFT (CVMX_L2C_IDX_ADDR_SHIFT + cvmx_l2c_get_set_bits())
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#define CVMX_L2C_ALIAS_MASK (CVMX_L2C_IDX_MASK << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT)
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#define CVMX_L2C_MEMBANK_SELECT_SIZE 4096
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/* Defines for Virtualizations, valid only from Octeon II onwards. */
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#define CVMX_L2C_VRT_MAX_VIRTID_ALLOWED ((OCTEON_IS_MODEL(OCTEON_CN63XX)) ? 64 : 0)
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#define CVMX_L2C_VRT_MAX_MEMSZ_ALLOWED ((OCTEON_IS_MODEL(OCTEON_CN63XX)) ? 32 : 0)
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union cvmx_l2c_tag {
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uint64_t u64;
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struct {
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uint64_t reserved:28;
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uint64_t V:1; /* Line valid */
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uint64_t D:1; /* Line dirty */
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uint64_t L:1; /* Line locked */
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uint64_t U:1; /* Use, LRU eviction */
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uint64_t addr:32; /* Phys mem (not all bits valid) */
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} s;
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};
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/* Number of L2C Tag-and-data sections (TADs) that are connected to LMC. */
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#define CVMX_L2C_TADS 1
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/* L2C Performance Counter events. */
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enum cvmx_l2c_event {
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CVMX_L2C_EVENT_CYCLES = 0,
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CVMX_L2C_EVENT_INSTRUCTION_MISS = 1,
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CVMX_L2C_EVENT_INSTRUCTION_HIT = 2,
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CVMX_L2C_EVENT_DATA_MISS = 3,
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CVMX_L2C_EVENT_DATA_HIT = 4,
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CVMX_L2C_EVENT_MISS = 5,
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CVMX_L2C_EVENT_HIT = 6,
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CVMX_L2C_EVENT_VICTIM_HIT = 7,
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CVMX_L2C_EVENT_INDEX_CONFLICT = 8,
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CVMX_L2C_EVENT_TAG_PROBE = 9,
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CVMX_L2C_EVENT_TAG_UPDATE = 10,
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CVMX_L2C_EVENT_TAG_COMPLETE = 11,
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CVMX_L2C_EVENT_TAG_DIRTY = 12,
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CVMX_L2C_EVENT_DATA_STORE_NOP = 13,
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CVMX_L2C_EVENT_DATA_STORE_READ = 14,
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CVMX_L2C_EVENT_DATA_STORE_WRITE = 15,
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CVMX_L2C_EVENT_FILL_DATA_VALID = 16,
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CVMX_L2C_EVENT_WRITE_REQUEST = 17,
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CVMX_L2C_EVENT_READ_REQUEST = 18,
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CVMX_L2C_EVENT_WRITE_DATA_VALID = 19,
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CVMX_L2C_EVENT_XMC_NOP = 20,
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CVMX_L2C_EVENT_XMC_LDT = 21,
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CVMX_L2C_EVENT_XMC_LDI = 22,
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CVMX_L2C_EVENT_XMC_LDD = 23,
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CVMX_L2C_EVENT_XMC_STF = 24,
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CVMX_L2C_EVENT_XMC_STT = 25,
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CVMX_L2C_EVENT_XMC_STP = 26,
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CVMX_L2C_EVENT_XMC_STC = 27,
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CVMX_L2C_EVENT_XMC_DWB = 28,
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CVMX_L2C_EVENT_XMC_PL2 = 29,
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CVMX_L2C_EVENT_XMC_PSL1 = 30,
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CVMX_L2C_EVENT_XMC_IOBLD = 31,
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CVMX_L2C_EVENT_XMC_IOBST = 32,
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CVMX_L2C_EVENT_XMC_IOBDMA = 33,
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CVMX_L2C_EVENT_XMC_IOBRSP = 34,
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CVMX_L2C_EVENT_XMC_BUS_VALID = 35,
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CVMX_L2C_EVENT_XMC_MEM_DATA = 36,
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CVMX_L2C_EVENT_XMC_REFL_DATA = 37,
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CVMX_L2C_EVENT_XMC_IOBRSP_DATA = 38,
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CVMX_L2C_EVENT_RSC_NOP = 39,
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CVMX_L2C_EVENT_RSC_STDN = 40,
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CVMX_L2C_EVENT_RSC_FILL = 41,
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CVMX_L2C_EVENT_RSC_REFL = 42,
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CVMX_L2C_EVENT_RSC_STIN = 43,
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CVMX_L2C_EVENT_RSC_SCIN = 44,
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CVMX_L2C_EVENT_RSC_SCFL = 45,
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CVMX_L2C_EVENT_RSC_SCDN = 46,
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CVMX_L2C_EVENT_RSC_DATA_VALID = 47,
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CVMX_L2C_EVENT_RSC_VALID_FILL = 48,
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CVMX_L2C_EVENT_RSC_VALID_STRSP = 49,
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CVMX_L2C_EVENT_RSC_VALID_REFL = 50,
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CVMX_L2C_EVENT_LRF_REQ = 51,
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CVMX_L2C_EVENT_DT_RD_ALLOC = 52,
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CVMX_L2C_EVENT_DT_WR_INVAL = 53,
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CVMX_L2C_EVENT_MAX
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};
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/* L2C Performance Counter events for Octeon2. */
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enum cvmx_l2c_tad_event {
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CVMX_L2C_TAD_EVENT_NONE = 0,
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CVMX_L2C_TAD_EVENT_TAG_HIT = 1,
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CVMX_L2C_TAD_EVENT_TAG_MISS = 2,
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CVMX_L2C_TAD_EVENT_TAG_NOALLOC = 3,
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CVMX_L2C_TAD_EVENT_TAG_VICTIM = 4,
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CVMX_L2C_TAD_EVENT_SC_FAIL = 5,
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CVMX_L2C_TAD_EVENT_SC_PASS = 6,
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CVMX_L2C_TAD_EVENT_LFB_VALID = 7,
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CVMX_L2C_TAD_EVENT_LFB_WAIT_LFB = 8,
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CVMX_L2C_TAD_EVENT_LFB_WAIT_VAB = 9,
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CVMX_L2C_TAD_EVENT_QUAD0_INDEX = 128,
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CVMX_L2C_TAD_EVENT_QUAD0_READ = 129,
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CVMX_L2C_TAD_EVENT_QUAD0_BANK = 130,
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CVMX_L2C_TAD_EVENT_QUAD0_WDAT = 131,
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CVMX_L2C_TAD_EVENT_QUAD1_INDEX = 144,
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CVMX_L2C_TAD_EVENT_QUAD1_READ = 145,
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CVMX_L2C_TAD_EVENT_QUAD1_BANK = 146,
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CVMX_L2C_TAD_EVENT_QUAD1_WDAT = 147,
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CVMX_L2C_TAD_EVENT_QUAD2_INDEX = 160,
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CVMX_L2C_TAD_EVENT_QUAD2_READ = 161,
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CVMX_L2C_TAD_EVENT_QUAD2_BANK = 162,
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CVMX_L2C_TAD_EVENT_QUAD2_WDAT = 163,
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CVMX_L2C_TAD_EVENT_QUAD3_INDEX = 176,
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CVMX_L2C_TAD_EVENT_QUAD3_READ = 177,
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CVMX_L2C_TAD_EVENT_QUAD3_BANK = 178,
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CVMX_L2C_TAD_EVENT_QUAD3_WDAT = 179,
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CVMX_L2C_TAD_EVENT_MAX
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};
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/**
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* Configure one of the four L2 Cache performance counters to capture event
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* occurrences.
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*
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* @counter: The counter to configure. Range 0..3.
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* @event: The type of L2 Cache event occurrence to count.
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* @clear_on_read: When asserted, any read of the performance counter
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* clears the counter.
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*
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* @note The routine does not clear the counter.
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*/
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void cvmx_l2c_config_perf(uint32_t counter, enum cvmx_l2c_event event, uint32_t clear_on_read);
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/**
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* Read the given L2 Cache performance counter. The counter must be configured
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* before reading, but this routine does not enforce this requirement.
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*
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* @counter: The counter to configure. Range 0..3.
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*
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* Returns The current counter value.
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*/
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uint64_t cvmx_l2c_read_perf(uint32_t counter);
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/**
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* Return the L2 Cache way partitioning for a given core.
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*
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* @core: The core processor of interest.
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*
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* Returns The mask specifying the partitioning. 0 bits in mask indicates
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* the cache 'ways' that a core can evict from.
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* -1 on error
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*/
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int cvmx_l2c_get_core_way_partition(uint32_t core);
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/**
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* Partitions the L2 cache for a core
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*
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* @core: The core that the partitioning applies to.
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* @mask: The partitioning of the ways expressed as a binary
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* mask. A 0 bit allows the core to evict cache lines from
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* a way, while a 1 bit blocks the core from evicting any
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* lines from that way. There must be at least one allowed
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* way (0 bit) in the mask.
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*
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* @note If any ways are blocked for all cores and the HW blocks, then
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* those ways will never have any cache lines evicted from them.
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* All cores and the hardware blocks are free to read from all
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* ways regardless of the partitioning.
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*/
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int cvmx_l2c_set_core_way_partition(uint32_t core, uint32_t mask);
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/**
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* Return the L2 Cache way partitioning for the hw blocks.
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*
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* Returns The mask specifying the reserved way. 0 bits in mask indicates
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* the cache 'ways' that a core can evict from.
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* -1 on error
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*/
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int cvmx_l2c_get_hw_way_partition(void);
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/**
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* Partitions the L2 cache for the hardware blocks.
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*
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* @mask: The partitioning of the ways expressed as a binary
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* mask. A 0 bit allows the core to evict cache lines from
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* a way, while a 1 bit blocks the core from evicting any
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* lines from that way. There must be at least one allowed
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* way (0 bit) in the mask.
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*
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* @note If any ways are blocked for all cores and the HW blocks, then
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* those ways will never have any cache lines evicted from them.
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* All cores and the hardware blocks are free to read from all
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* ways regardless of the partitioning.
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*/
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int cvmx_l2c_set_hw_way_partition(uint32_t mask);
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/**
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* Locks a line in the L2 cache at the specified physical address
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*
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* @addr: physical address of line to lock
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*
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* Returns 0 on success,
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* 1 if line not locked.
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*/
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int cvmx_l2c_lock_line(uint64_t addr);
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/**
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* Locks a specified memory region in the L2 cache.
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*
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* Note that if not all lines can be locked, that means that all
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* but one of the ways (associations) available to the locking
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* core are locked. Having only 1 association available for
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* normal caching may have a significant adverse affect on performance.
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* Care should be taken to ensure that enough of the L2 cache is left
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* unlocked to allow for normal caching of DRAM.
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*
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* @start: Physical address of the start of the region to lock
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* @len: Length (in bytes) of region to lock
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*
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* Returns Number of requested lines that where not locked.
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* 0 on success (all locked)
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*/
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int cvmx_l2c_lock_mem_region(uint64_t start, uint64_t len);
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/**
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* Unlock and flush a cache line from the L2 cache.
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* IMPORTANT: Must only be run by one core at a time due to use
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* of L2C debug features.
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* Note that this function will flush a matching but unlocked cache line.
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* (If address is not in L2, no lines are flushed.)
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*
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* @address: Physical address to unlock
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*
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* Returns 0: line not unlocked
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* 1: line unlocked
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*/
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int cvmx_l2c_unlock_line(uint64_t address);
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/**
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* Unlocks a region of memory that is locked in the L2 cache
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*
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* @start: start physical address
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* @len: length (in bytes) to unlock
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*
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* Returns Number of locked lines that the call unlocked
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*/
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int cvmx_l2c_unlock_mem_region(uint64_t start, uint64_t len);
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/**
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* Read the L2 controller tag for a given location in L2
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*
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* @association:
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* Which association to read line from
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* @index: Which way to read from.
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*
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* Returns l2c tag structure for line requested.
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*/
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union cvmx_l2c_tag cvmx_l2c_get_tag(uint32_t association, uint32_t index);
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/* Wrapper providing a deprecated old function name */
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static inline union cvmx_l2c_tag cvmx_get_l2c_tag(uint32_t association, uint32_t index) __attribute__((deprecated));
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static inline union cvmx_l2c_tag cvmx_get_l2c_tag(uint32_t association, uint32_t index)
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{
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return cvmx_l2c_get_tag(association, index);
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}
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/**
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* Returns the cache index for a given physical address
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*
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* @addr: physical address
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*
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* Returns L2 cache index
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*/
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uint32_t cvmx_l2c_address_to_index(uint64_t addr);
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/**
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* Flushes (and unlocks) the entire L2 cache.
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* IMPORTANT: Must only be run by one core at a time due to use
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* of L2C debug features.
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*/
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void cvmx_l2c_flush(void);
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/**
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*
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* Returns Returns the size of the L2 cache in bytes,
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* -1 on error (unrecognized model)
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*/
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int cvmx_l2c_get_cache_size_bytes(void);
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/**
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* Return the number of sets in the L2 Cache
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*
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* Returns
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*/
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int cvmx_l2c_get_num_sets(void);
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/**
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* Return log base 2 of the number of sets in the L2 cache
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* Returns
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*/
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int cvmx_l2c_get_set_bits(void);
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/**
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* Return the number of associations in the L2 Cache
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*
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* Returns
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*/
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int cvmx_l2c_get_num_assoc(void);
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/**
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* Flush a line from the L2 cache
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* This should only be called from one core at a time, as this routine
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* sets the core to the 'debug' core in order to flush the line.
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*
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* @assoc: Association (or way) to flush
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* @index: Index to flush
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*/
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void cvmx_l2c_flush_line(uint32_t assoc, uint32_t index);
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#endif /* __CVMX_L2C_H__ */
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