199 lines
5.9 KiB
C
199 lines
5.9 KiB
C
/*
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* Pb1500 board support.
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*
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* Copyright (C) 2009 Manuel Lauss
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/gpio.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <asm/mach-au1x00/au1000.h>
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#include <asm/mach-db1x00/bcsr.h>
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#include <prom.h>
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#include "platform.h"
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const char *get_system_type(void)
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{
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return "PB1500";
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}
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void __init board_setup(void)
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{
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u32 pin_func;
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u32 sys_freqctrl, sys_clksrc;
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bcsr_init(DB1000_BCSR_PHYS_ADDR,
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DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS);
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sys_clksrc = sys_freqctrl = pin_func = 0;
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/* Set AUX clock to 12 MHz * 8 = 96 MHz */
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au_writel(8, SYS_AUXPLL);
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alchemy_gpio1_input_enable();
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udelay(100);
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/* GPIO201 is input for PCMCIA card detect */
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/* GPIO203 is input for PCMCIA interrupt request */
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alchemy_gpio_direction_input(201);
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alchemy_gpio_direction_input(203);
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#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
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/* Zero and disable FREQ2 */
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sys_freqctrl = au_readl(SYS_FREQCTRL0);
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sys_freqctrl &= ~0xFFF00000;
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au_writel(sys_freqctrl, SYS_FREQCTRL0);
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/* zero and disable USBH/USBD clocks */
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sys_clksrc = au_readl(SYS_CLKSRC);
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sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
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SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
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au_writel(sys_clksrc, SYS_CLKSRC);
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sys_freqctrl = au_readl(SYS_FREQCTRL0);
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sys_freqctrl &= ~0xFFF00000;
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sys_clksrc = au_readl(SYS_CLKSRC);
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sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
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SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
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/* FREQ2 = aux/2 = 48 MHz */
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sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) | SYS_FC_FE2 | SYS_FC_FS2;
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au_writel(sys_freqctrl, SYS_FREQCTRL0);
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/*
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* Route 48MHz FREQ2 into USB Host and/or Device
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*/
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sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MUH_BIT;
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au_writel(sys_clksrc, SYS_CLKSRC);
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pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_USB;
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/* 2nd USB port is USB host */
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pin_func |= SYS_PF_USB;
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au_writel(pin_func, SYS_PINFUNC);
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#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
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#ifdef CONFIG_PCI
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{
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void __iomem *base =
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(void __iomem *)KSEG1ADDR(AU1500_PCI_PHYS_ADDR);
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/* Setup PCI bus controller */
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__raw_writel(0x00003fff, base + PCI_REG_CMEM);
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__raw_writel(0xf0000000, base + PCI_REG_MWMASK_DEV);
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__raw_writel(0, base + PCI_REG_MWBASE_REV_CCL);
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__raw_writel(0x02a00356, base + PCI_REG_STATCMD);
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__raw_writel(0x00003c04, base + PCI_REG_PARAM);
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__raw_writel(0x00000008, base + PCI_REG_MBAR);
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wmb();
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}
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#endif
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/* Enable sys bus clock divider when IDLE state or no bus activity. */
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au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
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/* Enable the RTC if not already enabled */
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if (!(au_readl(0xac000028) & 0x20)) {
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printk(KERN_INFO "enabling clock ...\n");
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au_writel((au_readl(0xac000028) | 0x20), 0xac000028);
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}
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/* Put the clock in BCD mode */
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if (au_readl(0xac00002c) & 0x4) { /* reg B */
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au_writel(au_readl(0xac00002c) & ~0x4, 0xac00002c);
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au_sync();
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}
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}
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/******************************************************************************/
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static int pb1500_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
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{
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if ((slot < 12) || (slot > 13) || pin == 0)
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return -1;
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if (slot == 12)
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return (pin == 1) ? AU1500_PCI_INTA : 0xff;
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if (slot == 13) {
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switch (pin) {
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case 1: return AU1500_PCI_INTA;
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case 2: return AU1500_PCI_INTB;
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case 3: return AU1500_PCI_INTC;
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case 4: return AU1500_PCI_INTD;
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}
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}
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return -1;
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}
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static struct resource alchemy_pci_host_res[] = {
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[0] = {
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.start = AU1500_PCI_PHYS_ADDR,
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.end = AU1500_PCI_PHYS_ADDR + 0xfff,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct alchemy_pci_platdata pb1500_pci_pd = {
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.board_map_irq = pb1500_map_pci_irq,
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.pci_cfg_set = PCI_CONFIG_AEN | PCI_CONFIG_R2H | PCI_CONFIG_R1H |
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PCI_CONFIG_CH |
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#if defined(__MIPSEB__)
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PCI_CONFIG_SIC_HWA_DAT | PCI_CONFIG_SM,
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#else
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0,
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#endif
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};
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static struct platform_device pb1500_pci_host = {
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.dev.platform_data = &pb1500_pci_pd,
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.name = "alchemy-pci",
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.id = 0,
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.num_resources = ARRAY_SIZE(alchemy_pci_host_res),
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.resource = alchemy_pci_host_res,
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};
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static int __init pb1500_dev_init(void)
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{
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int swapped;
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irq_set_irq_type(AU1500_GPIO9_INT, IRQF_TRIGGER_LOW); /* CD0# */
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irq_set_irq_type(AU1500_GPIO10_INT, IRQF_TRIGGER_LOW); /* CARD0 */
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irq_set_irq_type(AU1500_GPIO11_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
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irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
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irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
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irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
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irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
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irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
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/* PCMCIA. single socket, identical to Pb1100 */
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db1x_register_pcmcia_socket(
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AU1000_PCMCIA_ATTR_PHYS_ADDR,
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AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
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AU1000_PCMCIA_MEM_PHYS_ADDR,
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AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
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AU1000_PCMCIA_IO_PHYS_ADDR,
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AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
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AU1500_GPIO11_INT, AU1500_GPIO9_INT, /* card / insert */
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/*AU1500_GPIO10_INT*/0, 0, 0); /* stschg / eject / id */
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swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT;
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db1x_register_norflash(64 * 1024 * 1024, 4, swapped);
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platform_device_register(&pb1500_pci_host);
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return 0;
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}
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arch_initcall(pb1500_dev_init);
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