154 lines
3.7 KiB
C
154 lines
3.7 KiB
C
/*
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* OMAP4-specific DPLL control functions
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*
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* Copyright (C) 2011 Texas Instruments, Inc.
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* Rajendra Nayak
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/bitops.h>
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#include <plat/cpu.h>
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#include <plat/clock.h>
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#include "clock.h"
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#include "clock44xx.h"
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#include "cm-regbits-44xx.h"
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/* Supported only on OMAP4 */
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int omap4_dpllmx_gatectrl_read(struct clk *clk)
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{
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u32 v;
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u32 mask;
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if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
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return -EINVAL;
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mask = clk->flags & CLOCK_CLKOUTX2 ?
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OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
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OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
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v = __raw_readl(clk->clksel_reg);
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v &= mask;
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v >>= __ffs(mask);
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return v;
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}
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void omap4_dpllmx_allow_gatectrl(struct clk *clk)
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{
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u32 v;
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u32 mask;
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if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
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return;
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mask = clk->flags & CLOCK_CLKOUTX2 ?
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OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
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OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
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v = __raw_readl(clk->clksel_reg);
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/* Clear the bit to allow gatectrl */
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v &= ~mask;
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__raw_writel(v, clk->clksel_reg);
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}
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void omap4_dpllmx_deny_gatectrl(struct clk *clk)
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{
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u32 v;
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u32 mask;
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if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
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return;
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mask = clk->flags & CLOCK_CLKOUTX2 ?
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OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
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OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
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v = __raw_readl(clk->clksel_reg);
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/* Set the bit to deny gatectrl */
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v |= mask;
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__raw_writel(v, clk->clksel_reg);
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}
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const struct clkops clkops_omap4_dpllmx_ops = {
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.allow_idle = omap4_dpllmx_allow_gatectrl,
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.deny_idle = omap4_dpllmx_deny_gatectrl,
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};
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/**
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* omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit
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* @clk: struct clk * of the DPLL to compute the rate for
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*
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* Compute the output rate for the OMAP4 DPLL represented by @clk.
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* Takes the REGM4XEN bit into consideration, which is needed for the
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* OMAP4 ABE DPLL. Returns the DPLL's output rate (before M-dividers)
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* upon success, or 0 upon error.
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*/
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unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk)
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{
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u32 v;
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unsigned long rate;
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struct dpll_data *dd;
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if (!clk || !clk->dpll_data)
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return 0;
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dd = clk->dpll_data;
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rate = omap2_get_dpll_rate(clk);
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/* regm4xen adds a multiplier of 4 to DPLL calculations */
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v = __raw_readl(dd->control_reg);
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if (v & OMAP4430_DPLL_REGM4XEN_MASK)
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rate *= OMAP4430_REGM4XEN_MULT;
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return rate;
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}
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/**
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* omap4_dpll_regm4xen_round_rate - round DPLL rate, considering REGM4XEN bit
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* @clk: struct clk * of the DPLL to round a rate for
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* @target_rate: the desired rate of the DPLL
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*
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* Compute the rate that would be programmed into the DPLL hardware
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* for @clk if set_rate() were to be provided with the rate
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* @target_rate. Takes the REGM4XEN bit into consideration, which is
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* needed for the OMAP4 ABE DPLL. Returns the rounded rate (before
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* M-dividers) upon success, -EINVAL if @clk is null or not a DPLL, or
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* ~0 if an error occurred in omap2_dpll_round_rate().
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*/
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long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate)
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{
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u32 v;
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struct dpll_data *dd;
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long r;
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if (!clk || !clk->dpll_data)
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return -EINVAL;
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dd = clk->dpll_data;
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/* regm4xen adds a multiplier of 4 to DPLL calculations */
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v = __raw_readl(dd->control_reg) & OMAP4430_DPLL_REGM4XEN_MASK;
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if (v)
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target_rate = target_rate / OMAP4430_REGM4XEN_MULT;
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r = omap2_dpll_round_rate(clk, target_rate);
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if (r == ~0)
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return r;
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if (v)
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clk->dpll_data->last_rounded_rate *= OMAP4430_REGM4XEN_MULT;
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return clk->dpll_data->last_rounded_rate;
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}
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