224 lines
5.6 KiB
C
224 lines
5.6 KiB
C
/*
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* Copyright (c) 2012, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __ARCH_ARM_MACH_MSM_CPR_H
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#define __ARCH_ARM_MACH_MSM_CPR_H
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/* Register Offsets for RBCPR */
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/* RBCPR Gate Count and Target Registers */
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#define RBCPR_GCNT_TARGET(n) (0x60 + 4 * n)
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/* RBCPR Timer Control */
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#define RBCPR_TIMER_INTERVAL 0x44
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#define RBIF_TIMER_ADJUST 0x4C
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/* RBCPR Config Register */
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#define RBIF_LIMIT 0x48
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#define RBCPR_STEP_QUOT 0X80
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#define RBCPR_CTL 0x90
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#define RBIF_SW_VLEVEL 0x94
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#define RBIF_CONT_ACK_CMD 0x98
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#define RBIF_CONT_NACK_CMD 0x9C
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/* RBCPR Result status Register */
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#define RBCPR_RESULT_0 0xA0
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#define RBCPR_RESULT_1 0xA4
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#define RBCPR_QUOT_AVG 0x118
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/* RBCPR DEBUG Register */
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#define RBCPR_DEBUG1 0x120
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/* RBCPR Interrupt Control Register */
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#define RBIF_IRQ_EN(n) (0x100 + 4 * n)
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#define RBIF_IRQ_CLEAR 0x110
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#define RBIF_IRQ_STATUS 0x114
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/* Bit Mask Values */
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#define GCNT_M 0x003FF000
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#define TARGET_M 0x00000FFF
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#define SW_VLEVEL_M 0x0000003F
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#define UP_FLAG_M 0x00000010
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#define DOWN_FLAG_M 0x00000004
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#define CEILING_M 0x00000FC0
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#define FLOOR_M 0x0000003F
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#define LOOP_EN_M 0x00000001
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#define TIMER_M 0x00000008
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#define SW_AUTO_CONT_ACK_EN_M 0x00000020
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#define SW_AUTO_CONT_NACK_DN_EN_M 0x00000040
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#define HW_TO_PMIC_EN_M BIT(4)
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#define BUSY_M BIT(19)
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#define QUOT_SLOW_M 0x00FFF000
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#define UP_THRESHOLD_M 0x0F000000
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#define DN_THRESHOLD_M 0xF0000000
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/* Bit Values */
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#define ENABLE_CPR BIT(0)
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#define DISABLE_CPR 0x0
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#define ENABLE_TIMER BIT(3)
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#define DISABLE_TIMER 0x0
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#define SW_MODE 0x0
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#define SW_AUTO_CONT_ACK_EN BIT(5)
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#define SW_AUTO_CONT_NACK_DN_EN BIT(6)
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/* Shift Values */
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#define RBIF_CONS_DN_SHIFT (0x4)
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/* Test values for RBCPR RUMI Testing */
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#define GNT_CNT 0xC0
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#define TARGET 0xEFF
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#define CEILING_V 0x30
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#define FLOOR_V 0x15
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#define SW_LEVEL 0x20
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/* Interrupt Mask for All interrupt flags */
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#define INT_MASK (MIN_INT | DOWN_INT | MID_INT | UP_INT | MAX_INT)
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/* Number of oscilator in each sensor */
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#define NUM_OSC 8
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#define CPR_MODE 2
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/**
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* enum cpr_mode - Modes in which cpr is used
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*/
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enum cpr_mode {
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NORMAL_MODE = 0,
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TURBO_MODE,
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SVS_MODE,
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};
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/**
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* enum cpr_action - Cpr actions to be taken
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*/
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enum cpr_action {
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DOWN = 0,
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UP,
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};
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/**
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* enum cpr_interrupt
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*/
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enum cpr_interrupt {
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DONE_INT = BIT(0),
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MIN_INT = BIT(1),
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DOWN_INT = BIT(2),
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MID_INT = BIT(3),
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UP_INT = BIT(4),
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MAX_INT = BIT(5),
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};
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/**
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* struct msm_cpr_osc - Data for CPR ring oscillator
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* @gcnt: gate count value for the oscillator
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* @quot: target value for ring oscillator
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*/
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struct msm_cpr_osc {
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int gcnt;
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uint32_t quot;
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};
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/**
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* struct msm_cpr_mode - Data for CPR modes of operation
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* @msm_cpr_osc: structure for oscillator data
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* @ring_osc: ring oscillator of the sensor
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* @tgt_volt_offset: inital voltage offset from default value
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* @step_quot: step Quot for CPR calcuation
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*/
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struct msm_cpr_mode {
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struct msm_cpr_osc ring_osc_data[NUM_OSC];
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int ring_osc;
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int32_t tgt_volt_offset;
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uint32_t step_quot;
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uint32_t turbo_Vmax;
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uint32_t turbo_Vmin;
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uint32_t nom_Vmax;
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uint32_t nom_Vmin;
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uint32_t calibrated_uV;
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};
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/**
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* struct msm_cpr_config - Platform data for CPR configuration
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* @ref_clk_khz: clock value of CPR in KHz
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* @delay_us: timer delay in micro second
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* @irq_line: irq line to be use (0 or 1 or 2)
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* @msm_cpr_mode: structure for CPR mode data
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*/
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struct msm_cpr_config {
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unsigned long ref_clk_khz;
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unsigned long delay_us;
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int irq_line;
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struct msm_cpr_mode *cpr_mode_data;
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int min_down_step;
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uint32_t tgt_count_div_N; /* Target Cnt(Nom) = Target Cnt(Turbo) / N */
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uint32_t floor;
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uint32_t ceiling;
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uint32_t sw_vlevel;
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uint32_t up_threshold;
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uint32_t dn_threshold;
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uint32_t up_margin;
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uint32_t dn_margin;
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uint32_t max_nom_freq;
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uint32_t max_freq;
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uint32_t max_quot;
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bool disable_cpr;
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uint32_t step_size;
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uint32_t (*get_quot)(uint32_t max_quot, uint32_t max_freq,
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uint32_t new_freq);
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void (*clk_enable)(void);
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};
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/**
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* struct msm_cpr_config - CPR Registers
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*/
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struct msm_cpr_reg {
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uint32_t rbif_timer_interval;
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uint32_t rbif_int_en;
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uint32_t rbif_limit;
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uint32_t rbif_timer_adjust;
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uint32_t rbcpr_gcnt_target;
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uint32_t rbcpr_step_quot;
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uint32_t rbif_sw_level;
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uint32_t rbcpr_ctl;
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};
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#if defined(CONFIG_MSM_CPR) || defined(CONFIG_MSM_CPR_MODULE)
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/* msm_cpr_pm_resume: Used by Power Manager for Idle Power Collapse */
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void msm_cpr_pm_resume(void);
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/* msm_cpr_pm_suspend: Used by Power Manager for Idle Power Collapse */
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void msm_cpr_pm_suspend(void);
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/* msm_cpr_enable: Used by Power Manager for GDFS */
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void msm_cpr_enable(void);
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/* msm_cpr_disable: Used by Power Manager for GDFS */
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void msm_cpr_disable(void);
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#else
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/* msm_cpr_pm_resume: Used by Power Manager for Idle Power Collapse */
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void msm_cpr_pm_resume(void) { }
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/* msm_cpr_pm_suspend: Used by Power Manager for Idle Power Collapse */
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void msm_cpr_pm_suspend(void) { }
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/* msm_cpr_enable: Used by Power Manager for GDFS */
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void msm_cpr_enable(void) { }
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/* msm_cpr_disable: Used by Power Manager for GDFS */
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void msm_cpr_disable(void) { }
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#endif
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#ifdef CONFIG_DEBUG_FS
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int msm_cpr_debug_init(void *);
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#else
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static inline int msm_cpr_debug_init(void *) { return 0; }
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#endif
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#endif /* __ARCH_ARM_MACH_MSM_CPR_H */
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