73 lines
1.8 KiB
Plaintext
73 lines
1.8 KiB
Plaintext
* ARM architected timer
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ARM Cortex-A7 and Cortex-A15 have a per-core architected timer, which
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provides a per-cpu local timer.
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The timer is attached to a GIC to deliver its two per-processor
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interrupts (one for the secure mode, one for the non-secure mode).
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** CP15 Timer node properties:
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- compatible : Should be "arm,armv7-timer"
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- interrupts : One or two interrupts for secure and non-secure mode
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- clock-frequency : The frequency of the main counter, in Hz. Optional.
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Example:
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timer {
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compatible = "arm,armv7-timer"";
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interrupts = <1 13 0xf08 1 14 0xf08>;
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clock-frequency = <100000000>;
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};
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** Memory mapped timer node properties:
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- compatible : Should at least contain "arm,armv7-timer-mem".
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- clock-frequency : The frequency of the main counter, in Hz. Optional.
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- reg : The control frame base address.
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Note that #address-cells, #size-cells, and ranges shall be present to ensure
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the CPU can address the frame's registers.
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Each timer node has up to 8 frame sub-nodes with the following properties:
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- frame-number: 0 to 7.
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- interrupts : Interrupt list for physical and virtual timers in that order.
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The virtual timer interrupt is optional.
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- reg : The first and second view base addresses in that order. The second view
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base address is optional.
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- status : "disabled" indicates the frame is not available for use. Optional.
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Example:
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timer@f0000000 {
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compatible = "arm,armv7-timer-mem";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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reg = <0xf0000000 0x1000>;
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clock-frequency = <50000000>;
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frame0@f0001000 {
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frame-number = <0>
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interrupts = <0 13 0x8>,
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<0 14 0x8>;
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reg = <0xf0001000 0x1000>,
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<0xf0002000 0x1000>;
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};
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frame1@f0003000 {
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frame-number = <1>
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interrupts = <0 15 0x8>;
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reg = <0xf0003000 0x1000>;
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status = "disabled";
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};
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};
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