164 lines
5.0 KiB
C
164 lines
5.0 KiB
C
/*
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* Copyright (c) 2008 Travis Geiselbrecht
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files
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* (the "Software"), to deal in the Software without restriction,
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* including without limitation the rights to use, copy, modify, merge,
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* publish, distribute, sublicense, and/or sell copies of the Software,
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* and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <debug.h>
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#include <reg.h>
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#include <dev/uart.h>
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#include <platform/omap3.h>
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#include <target/debugconfig.h>
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struct uart_stat {
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addr_t base;
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uint shift;
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};
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static struct uart_stat uart[3] = {
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{ OMAP_UART1_BASE, 2 },
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{ OMAP_UART2_BASE, 2 },
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{ OMAP_UART3_BASE, 2 },
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};
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static inline void write_uart_reg(int port, uint reg, unsigned char data)
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{
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*(volatile unsigned char *)(uart[port].base + (reg << uart[port].shift)) = data;
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}
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static inline unsigned char read_uart_reg(int port, uint reg)
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{
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return *(volatile unsigned char *)(uart[port].base + (reg << uart[port].shift));
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}
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#define LCR_8N1 0x03
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#define FCR_FIFO_EN 0x01 /* Fifo enable */
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#define FCR_RXSR 0x02 /* Receiver soft reset */
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#define FCR_TXSR 0x04 /* Transmitter soft reset */
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#define MCR_DTR 0x01
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#define MCR_RTS 0x02
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#define MCR_DMA_EN 0x04
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#define MCR_TX_DFR 0x08
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#define LCR_WLS_MSK 0x03 /* character length select mask */
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#define LCR_WLS_5 0x00 /* 5 bit character length */
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#define LCR_WLS_6 0x01 /* 6 bit character length */
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#define LCR_WLS_7 0x02 /* 7 bit character length */
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#define LCR_WLS_8 0x03 /* 8 bit character length */
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#define LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */
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#define LCR_PEN 0x08 /* Parity eneble */
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#define LCR_EPS 0x10 /* Even Parity Select */
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#define LCR_STKP 0x20 /* Stick Parity */
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#define LCR_SBRK 0x40 /* Set Break */
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#define LCR_BKSE 0x80 /* Bank select enable */
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#define LSR_DR 0x01 /* Data ready */
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#define LSR_OE 0x02 /* Overrun */
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#define LSR_PE 0x04 /* Parity error */
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#define LSR_FE 0x08 /* Framing error */
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#define LSR_BI 0x10 /* Break */
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#define LSR_THRE 0x20 /* Xmit holding register empty */
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#define LSR_TEMT 0x40 /* Xmitter empty */
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#define LSR_ERR 0x80 /* Error */
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#define LCRVAL LCR_8N1 /* 8 data, 1 stop, no parity */
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#define MCRVAL (MCR_DTR | MCR_RTS) /* RTS/DTR */
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#define FCRVAL (FCR_FIFO_EN | FCR_RXSR | FCR_TXSR) /* Clear & enable FIFOs */
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#define V_NS16550_CLK (48000000) /* 48MHz (APLL96/2) */
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void uart_init_port(int port, uint baud)
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{
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/* clear the tx & rx fifo and disable */
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uint16_t baud_divisor = (V_NS16550_CLK / 16 / baud);
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write_uart_reg(port, UART_IER, 0);
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write_uart_reg(port, UART_LCR, LCR_BKSE | LCRVAL); // config mode A
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write_uart_reg(port, UART_DLL, baud_divisor & 0xff);
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write_uart_reg(port, UART_DLH, (baud_divisor >> 8) & 0xff);
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write_uart_reg(port, UART_LCR, LCRVAL); // operational mode
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write_uart_reg(port, UART_MCR, MCRVAL);
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write_uart_reg(port, UART_FCR, FCRVAL);
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write_uart_reg(port, UART_MDR1, 0); // UART 16x mode
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// write_uart_reg(port, UART_LCR, 0xBF); // config mode B
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// write_uart_reg(port, UART_EFR, (1<<7)|(1<<6)); // hw flow control
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// write_uart_reg(port, UART_LCR, LCRVAL); // operational mode
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}
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void uart_init_early(void)
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{
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/* UART1 */
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RMWREG32(CM_FCLKEN1_CORE, 13, 1, 1),
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RMWREG32(CM_ICLKEN1_CORE, 13, 1, 1),
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/* UART2 */
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RMWREG32(CM_FCLKEN1_CORE, 14, 1, 1),
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RMWREG32(CM_ICLKEN1_CORE, 14, 1, 1),
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/* UART3 */
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RMWREG32(CM_FCLKEN_PER, 11, 1, 1),
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RMWREG32(CM_ICLKEN_PER, 11, 1, 1),
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uart_init_port(DEBUG_UART, 115200);
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}
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void uart_init(void)
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{
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}
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int uart_putc(int port, char c )
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{
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while (!(read_uart_reg(port, UART_LSR) & (1<<6))) // wait for the last char to get out
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;
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write_uart_reg(port, UART_THR, c);
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return 0;
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}
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int uart_getc(int port, bool wait) /* returns -1 if no data available */
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{
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if (wait) {
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while (!(read_uart_reg(port, UART_LSR) & (1<<0))) // wait for data to show up in the rx fifo
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;
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} else {
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if (!(read_uart_reg(port, UART_LSR) & (1<<0)))
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return -1;
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}
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return read_uart_reg(port, UART_RHR);
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}
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void uart_flush_tx(int port)
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{
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while (!(read_uart_reg(port, UART_LSR) & (1<<6))) // wait for the last char to get out
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;
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}
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void uart_flush_rx(int port)
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{
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// empty the rx fifo
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while (read_uart_reg(port, UART_LSR) & (1<<0)) {
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volatile char c = read_uart_reg(port, UART_RHR);
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(void)c;
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}
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}
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