475 lines
11 KiB
C
475 lines
11 KiB
C
/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of The Linux Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <err.h>
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#include <assert.h>
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#include <debug.h>
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#include <reg.h>
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#include <platform/timer.h>
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#include <platform/iomap.h>
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#include <mmc.h>
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#include <clock.h>
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#include <platform/clock.h>
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#include <blsp_qup.h>
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void hsusb_clock_init(void)
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{
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int ret;
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struct clk *iclk, *cclk;
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ret = clk_get_set_enable("usb_iface_clk", 0, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set usb_iface_clk ret = %d\n", ret);
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ASSERT(0);
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}
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ret = clk_get_set_enable("usb_core_clk", 75000000, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set usb_core_clk ret = %d\n", ret);
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ASSERT(0);
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}
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mdelay(20);
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iclk = clk_get("usb_iface_clk");
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cclk = clk_get("usb_core_clk");
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clk_disable(iclk);
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clk_disable(cclk);
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mdelay(20);
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/* Start the block reset for usb */
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writel(1, USB_HS_BCR);
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mdelay(20);
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/* Take usb block out of reset */
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writel(0, USB_HS_BCR);
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mdelay(20);
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ret = clk_enable(iclk);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret);
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ASSERT(0);
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}
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ret = clk_enable(cclk);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret);
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ASSERT(0);
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}
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}
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void clock_init_mmc(uint32_t interface)
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{
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char clk_name[64];
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int ret;
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snprintf(clk_name, 64, "sdc%u_iface_clk", interface);
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/* enable interface clock */
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ret = clk_get_set_enable(clk_name, 0, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set sdc1_iface_clk ret = %d\n", ret);
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ASSERT(0);
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}
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}
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/* Configure MMC clock */
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void clock_config_mmc(uint32_t interface, uint32_t freq)
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{
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int ret;
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uint32_t reg;
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char clk_name[64];
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snprintf(clk_name, 64, "sdc%u_core_clk", interface);
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/* Disalbe MCI_CLK before changing the sdcc clock */
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#ifndef MMC_SDHCI_SUPPORT
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mmc_boot_mci_clk_disable();
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#endif
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if(freq == MMC_CLK_400KHZ)
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{
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ret = clk_get_set_enable(clk_name, 400000, 1);
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}
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else if(freq == MMC_CLK_50MHZ)
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{
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ret = clk_get_set_enable(clk_name, 50000000, 1);
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}
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else if(freq == MMC_CLK_96MHZ)
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{
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ret = clk_get_set_enable(clk_name, 100000000, 1);
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}
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else if(freq == MMC_CLK_200MHZ)
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{
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ret = clk_get_set_enable(clk_name, 200000000, 1);
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}
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else
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{
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dprintf(CRITICAL, "sdc frequency (%d) is not supported\n", freq);
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ASSERT(0);
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}
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if(ret)
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{
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dprintf(CRITICAL, "failed to set sdc1_core_clk ret = %d\n", ret);
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ASSERT(0);
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}
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/* Enalbe MCI clock */
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#ifndef MMC_SDHCI_SUPPORT
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mmc_boot_mci_clk_enable();
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#endif
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}
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/* Configure UART clock based on the UART block id*/
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void clock_config_uart_dm(uint8_t id)
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{
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int ret;
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ret = clk_get_set_enable("uart2_iface_clk", 0, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set uart2_iface_clk ret = %d\n", ret);
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ASSERT(0);
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}
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ret = clk_get_set_enable("uart2_core_clk", 7372800, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set uart1_core_clk ret = %d\n", ret);
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ASSERT(0);
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}
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}
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/* Function to asynchronously reset CE.
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* Function assumes that all the CE clocks are off.
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*/
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static void ce_async_reset(uint8_t instance)
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{
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if (instance == 1)
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{
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/* TODO: Add support for instance 1. */
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dprintf(CRITICAL, "CE instance not supported instance = %d", instance);
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ASSERT(0);
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}
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else if (instance == 2)
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{
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/* Start the block reset for CE */
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writel(1, GCC_CE2_BCR);
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udelay(2);
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/* Take CE block out of reset */
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writel(0, GCC_CE2_BCR);
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udelay(2);
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}
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else
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{
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dprintf(CRITICAL, "CE instance not supported instance = %d", instance);
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ASSERT(0);
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}
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}
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void clock_ce_enable(uint8_t instance)
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{
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int ret;
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char clk_name[64];
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snprintf(clk_name, 64, "ce%u_src_clk", instance);
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ret = clk_get_set_enable(clk_name, 100000000, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set ce_src_clk ret = %d\n", ret);
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ASSERT(0);
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}
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snprintf(clk_name, 64, "ce%u_core_clk", instance);
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ret = clk_get_set_enable(clk_name, 0, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set ce_core_clk ret = %d\n", ret);
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ASSERT(0);
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}
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snprintf(clk_name, 64, "ce%u_ahb_clk", instance);
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ret = clk_get_set_enable(clk_name, 0, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set ce_ahb_clk ret = %d\n", ret);
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ASSERT(0);
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}
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snprintf(clk_name, 64, "ce%u_axi_clk", instance);
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ret = clk_get_set_enable(clk_name, 0, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set ce_axi_clk ret = %d\n", ret);
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ASSERT(0);
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}
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/* Wait for 48 * #pipes cycles.
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* This is necessary as immediately after an access control reset (boot up)
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* or a debug re-enable, the Crypto core sequentially clears its internal
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* pipe key storage memory. If pipe key initialization writes are attempted
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* during this time, they may be overwritten by the internal clearing logic.
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*/
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udelay(1);
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}
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void clock_ce_disable(uint8_t instance)
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{
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struct clk *ahb_clk;
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struct clk *cclk;
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struct clk *axi_clk;
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struct clk *src_clk;
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char clk_name[64];
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snprintf(clk_name, 64, "ce%u_src_clk", instance);
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src_clk = clk_get(clk_name);
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snprintf(clk_name, 64, "ce%u_ahb_clk", instance);
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ahb_clk = clk_get(clk_name);
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snprintf(clk_name, 64, "ce%u_axi_clk", instance);
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axi_clk = clk_get(clk_name);
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snprintf(clk_name, 64, "ce%u_core_clk", instance);
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cclk = clk_get(clk_name);
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clk_disable(ahb_clk);
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clk_disable(axi_clk);
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clk_disable(cclk);
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clk_disable(src_clk);
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/* Some delay for the clocks to stabalize. */
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udelay(1);
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}
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void clock_config_ce(uint8_t instance)
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{
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/* Need to enable the clock before disabling since the clk_disable()
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* has a check to default to nop when the clk_enable() is not called
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* on that particular clock.
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*/
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clock_ce_enable(instance);
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clock_ce_disable(instance);
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ce_async_reset(instance);
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clock_ce_enable(instance);
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}
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void clock_config_blsp_i2c(uint8_t blsp_id, uint8_t qup_id)
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{
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uint8_t ret = 0;
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char clk_name[64];
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struct clk *qup_clk;
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snprintf(clk_name, 64, "blsp%u_ahb_clk", blsp_id);
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ret = clk_get_set_enable(clk_name, 0 , 1);
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if (ret) {
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dprintf(CRITICAL, "Failed to enable %s clock\n", clk_name);
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return;
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}
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snprintf(clk_name, 64, "blsp%u_qup%u_i2c_apps_clk", blsp_id,
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(qup_id + 1));
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qup_clk = clk_get(clk_name);
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if (!qup_clk) {
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dprintf(CRITICAL, "Failed to get %s\n", clk_name);
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return;
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}
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ret = clk_enable(qup_clk);
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if (ret) {
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dprintf(CRITICAL, "Failed to enable %s\n", clk_name);
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return;
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}
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}
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void mdp_gdsc_ctrl(uint8_t enable)
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{
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uint32_t reg = 0;
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reg = readl(MDP_GDSCR);
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if (enable) {
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if (reg & 0x1) {
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reg &= ~(BIT(0) | GDSC_EN_FEW_WAIT_MASK);
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reg |= GDSC_EN_FEW_WAIT_256_MASK;
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writel(reg, MDP_GDSCR);
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}
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while(readl(MDP_GDSCR) & ((GDSC_POWER_ON_BIT) | (GDSC_POWER_ON_STATUS_BIT)));
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} else {
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reg &= ~BIT(0);
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writel(reg, MDP_GDSCR);
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while(!(readl(MDP_GDSCR) & ((GDSC_POWER_ON_BIT))));
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}
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}
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/* Configure MDP clock */
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void mdp_clock_init(void)
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{
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int ret;
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/* Set MDP clock to 200MHz */
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ret = clk_get_set_enable("mdp_ahb_clk", 0, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set mdp_ahb_clk ret = %d\n", ret);
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ASSERT(0);
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}
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ret = clk_get_set_enable("mdss_mdp_clk_src", 75000000, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set mdp_clk_src ret = %d\n", ret);
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ASSERT(0);
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}
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ret = clk_get_set_enable("mdss_vsync_clk", 0, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set mdss vsync clk ret = %d\n", ret);
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ASSERT(0);
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}
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ret = clk_get_set_enable("mdss_mdp_clk", 0, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set mdp_clk ret = %d\n", ret);
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ASSERT(0);
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}
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ret = clk_get_set_enable("mdss_mdp_lut_clk", 0, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set lut_mdp clk ret = %d\n", ret);
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ASSERT(0);
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}
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}
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void mdp_clock_disable(void)
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{
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writel(0x0, DSI_BYTE0_CBCR);
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writel(0x0, DSI_PIXEL0_CBCR);
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clk_disable(clk_get("mdss_vsync_clk"));
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clk_disable(clk_get("mdss_mdp_clk"));
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clk_disable(clk_get("mdss_mdp_lut_clk"));
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clk_disable(clk_get("mdss_mdp_clk_src"));
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clk_disable(clk_get("mdp_ahb_clk"));
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}
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/* Initialize all clocks needed by Display */
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void mmss_clock_init(uint32_t dsi_pixel0_cfg_rcgr)
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{
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int ret;
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/* Configure Byte clock */
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writel(0x100, DSI_BYTE0_CFG_RCGR);
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writel(0x1, DSI_BYTE0_CMD_RCGR);
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writel(0x1, DSI_BYTE0_CBCR);
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/* Configure ESC clock */
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ret = clk_get_set_enable("mdss_esc0_clk", 0, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set esc0_clk ret = %d\n", ret);
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ASSERT(0);
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}
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/* Configure MMSSNOC AXI clock */
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ret = clk_get_set_enable("mmss_mmssnoc_axi_clk", 100000000, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set mmssnoc_axi_clk ret = %d\n", ret);
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ASSERT(0);
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}
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/* Configure MMSSNOC AXI clock */
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ret = clk_get_set_enable("mmss_s0_axi_clk", 100000000, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set mmss_s0_axi_clk ret = %d\n", ret);
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ASSERT(0);
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}
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/* Configure AXI clock */
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ret = clk_get_set_enable("mdss_axi_clk", 100000000, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set mdss_axi_clk ret = %d\n", ret);
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ASSERT(0);
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}
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/* Configure Pixel clock */
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writel(dsi_pixel0_cfg_rcgr, DSI_PIXEL0_CFG_RCGR);
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writel(0x1, DSI_PIXEL0_CMD_RCGR);
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writel(0x1, DSI_PIXEL0_CBCR);
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}
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void mmss_clock_disable(void)
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{
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/* Disable ESC clock */
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clk_disable(clk_get("mdss_esc0_clk"));
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/* Disable MDSS AXI clock */
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clk_disable(clk_get("mdss_axi_clk"));
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/* Disable MMSSNOC S0AXI clock */
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clk_disable(clk_get("mmss_s0_axi_clk"));
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/* Disable MMSSNOC AXI clock */
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clk_disable(clk_get("mmss_mmssnoc_axi_clk"));
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}
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