190 lines
4.6 KiB
C
Executable File
190 lines
4.6 KiB
C
Executable File
/*
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* Copyright (c) 2008, Google Inc.
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* All rights reserved.
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* Copyright (c) 2009-2011, The Linux Foundation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Google, Inc. nor the names of its contributors
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* may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <debug.h>
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#include <reg.h>
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#include <dev/fbcon.h>
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#include <kernel/thread.h>
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#include <platform/debug.h>
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#include <platform/iomap.h>
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#include <mddi_hw.h>
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#include "gpio_hw.h"
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#include <dev/lcdc.h>
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void platform_init_interrupts(void);
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void platform_init_timer();
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void uart2_clock_init(void);
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void uart_init(void);
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struct fbcon_config *lcdc_init(void);
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static uint32_t ticks_per_sec = 0;
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#define ARRAY_SIZE(a) (sizeof(a)/(sizeof((a)[0])))
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static unsigned uart2_gpio_table[] = {
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GPIO_CFG(49, 2, GPIO_OUTPUT, GPIO_PULL_DOWN, GPIO_2MA),
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GPIO_CFG(50, 2, GPIO_INPUT, GPIO_PULL_DOWN, GPIO_2MA),
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GPIO_CFG(51, 2, GPIO_INPUT, GPIO_PULL_DOWN, GPIO_2MA),
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GPIO_CFG(52, 2, GPIO_OUTPUT, GPIO_PULL_DOWN, GPIO_2MA),
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};
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/* CRCI - mmc slot mapping.
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* mmc slot numbering start from 1.
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* entry at index 0 is just dummy.
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*/
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uint8_t sdc_crci_map[5] = { 0, 6, 7, 12, 13 };
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void uart2_mux_init(void)
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{
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platform_gpios_enable(uart2_gpio_table, ARRAY_SIZE(uart2_gpio_table));
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}
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void platform_early_init(void)
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{
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#if WITH_DEBUG_UART
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uart2_mux_init();
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uart2_clock_init();
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uart_init();
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#endif
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platform_init_interrupts();
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platform_init_timer();
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}
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void platform_init(void)
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{
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struct fbcon_config *fb_cfg;
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dprintf(INFO, "platform_init()\n");
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acpu_clock_init();
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adm_enable_clock();
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}
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void mdp4_display_intf_sel(int output, int intf)
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{
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unsigned bits, mask;
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unsigned dma2_cfg_reg;
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bits = readl(MSM_MDP_BASE1 + 0x0038);
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mask = 0x03; /* 2 bits */
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intf &= 0x03; /* 2 bits */
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switch (output) {
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case EXTERNAL_INTF_SEL:
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intf <<= 4;
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mask <<= 4;
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break;
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case SECONDARY_INTF_SEL:
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intf &= 0x02; /* only MDDI and EBI2 support */
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intf <<= 2;
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mask <<= 2;
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break;
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default:
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break;
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}
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bits &= ~mask;
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bits |= intf;
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writel(bits, MSM_MDP_BASE1 + 0x0038); /* MDP_DISP_INTF_SEL */
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}
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void display_init(void)
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{
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struct fbcon_config *fb_cfg;
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#if DISPLAY_TYPE_MDDI
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mddi_pmdh_clock_init();
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mddi_panel_poweron();
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/* We need to config GPIO 38 for Sleep clock with Spl Fun 2 */
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toshiba_pmic_gpio_init(GPIO38_GPIO_CNTRL);
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fb_cfg = mddi_init();
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fbcon_setup(fb_cfg);
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#endif
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#if DISPLAY_TYPE_LCDC
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if(!machine_is_ffa()) {
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struct lcdc_timing_parameters *lcd_timing;
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mdp_lcdc_clock_init();
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lcd_timing = get_lcd_timing();
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fb_cfg = lcdc_init_set(lcd_timing);
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panel_poweron();
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fbcon_setup(fb_cfg);
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}
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#endif
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}
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void display_shutdown(void)
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{
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#if DISPLAY_TYPE_LCDC
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/* Turning off LCDC */
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if(!machine_is_ffa()) {
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lcdc_shutdown();
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}
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#endif
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}
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void platform_uninit(void)
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{
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#if DISPLAY_SPLASH_SCREEN
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display_shutdown();
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#endif
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platform_uninit_timer();
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}
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/* Initialize DGT timer */
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void platform_init_timer(void)
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{
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uint32_t val = 0;
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/* Disable timer */
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writel(0, DGT_ENABLE);
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/* Check for the hardware revision */
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val = readl(HW_REVISION_NUMBER);
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val = (val >> 28) & 0x0F;
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if (val >= 1)
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writel(1, DGT_CLK_CTL);
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#if _EMMC_BOOT
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ticks_per_sec = 19200000; /* Uses TCXO (19.2 MHz) */
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#else
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ticks_per_sec = 6144000; /* Uses LPXO/4 (24.576 MHz / 4) */
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#endif
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}
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/* Returns platform specific ticks per sec */
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uint32_t platform_tick_rate(void)
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{
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return ticks_per_sec;
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}
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